SU1341651A2 - Histogram forming device - Google Patents

Abstract

The invention relates to computing and measurement technology and can be used to analyze the distribution of random processes. The purpose of the invention is to expand the functionality of the device by quantizing the process of the act- Lenin single events in real time. Quantization (quantification) is performed using the newly introduced event number counter, the comparison circuit of the number of quantization intervals, the OR element, the register of the quantization interval value, and the delay element. Quantification occurs sequentially, a histogram is formed over time, then by the number of events. This makes it possible to construct histograms for a quantified process of receiving single events. 1 il. с со i О) ate N)

Description

The image relates to the computing and measuring technique, can be used to analyze the distribution of random processes and is an improvement of the device according to the author. St. K 1038950.

The purpose of the invention is to expand the functionality by quantizing the process of receiving single events in real time.

The drawing schematically shows the proposed device.

The device contains a counter 1 of the number of quantization intervals, a comparison circuit 2, a register 3 values of a quantization interval, a delay element 4, a counter of 5 numbers of events, N registers 6 interval boundaries, N comparison schemes 7, a group of N + 1 elements AND 8, a group of N + 1 counters 9, counter 10 the number of histogram formations, a group of N + 1 elements And 11, a delay element 12, a trigger 13, an element And 14, a counter 15 of interrogation pulses, a decoder 16, elements OR 17, a group of elements AND 18, a division block 19, a block 20 memories, the corresponding inputs 21-26 of the device, the register 27 of receiving the number and the ele UNT OR 28.

The device works as follows

For quantization (quantification) by time in the initial state, register 3 recorded the value of the quantification interval, registers 6 sequentially recorded numbers from 1 to the number of events N, upon receipt of which you can make an assumption about the nature of the process, counters 1, 5 9, 10 and 15 and trigger 13 are set to O.

The input 21 is supplied with a sequence of clock pulses with a frequency that provides the required accuracy of quantification intervals. At the entrance of the 23 impulses received moments of occurrence of events. Thus, the circuit works while the value of counter 1 is less than the value of register 3. When the value of counter 1 of the number of quantization intervals becomes equal to the value of register 3, the comparison circuit 2 is triggered and the enabling signal is fed to the input of counter Yu, increasing its value by one, to the group inputs elements and 8. Values

counter 5, equal to the number of events received during the grouping interval, is fed to the input of comparison circuits 7 through register 27 from the input of delay element 4, passed through it, the output from circuit 2 arrives to the input of counters 1 and 5, transferring them to O.

The order of operation of the device is explained for three cases where the value of the counter 5

equal to X 1

UX ,, $ N,

X N. Upon receipt of the first

(

due to the condition of the first output of the first circuit

 one

7, the resolving potential is fed to the input of the first element AND 8, and the signal arriving at the input of elements AND 8 from the output of circuit 2 of the comparison passes through the open element AND 8 to the input of the first counter 9, increasing its value by one.

If counter 5 is equal to x, two adjacent circuits 7 are found with numbers i-1 and i, which establish the fact of inequality x i-1, in this case from the second output of the first and from the first output of the second one the input of the i-ro element And 8 resolving potentials. The signal from the output of the comparison circuit 2 through the open i-th element I 8 passes to the input of the i-ro counter 9, increasing its content by one.

If the value of the counter 5 equals the number Xd due to the fulfillment of the condition Xs N from the second output of the Nth comparison circuit 7, the resolving potential is applied to the (H + 1) -th element of And 8. Sig-. cash received from the output of scheme 2. comparison through the open element And 8, is fed to the input of (N + 1) -ro counter 9, increasing its content by one.

This is how histogram is generated.

The histogram normalization signal is fed to input 25, switching trigger 13 to state 1 and allowing incoming polling pulses from input 26 through AND 14 to the input of counter 15. The arrival of the i-th pulse (i 1, N) in SC61TCHIC 15 causes the appearance the signal at the 1st output of the decoder 16 that allows you to rewrite the contents of the i-ro counter 9 through the i-th group of elements AND 11, the block of elements OR 17 to the input of the block 19

3

division. The result of dividing from the output of block 19 through the i-th element of group 18 and 18 enters the i-th cell of memory block 20. When a (N + 1) -ro pulse arrives, in addition, the signal from the last output of the decoder 16, delayed by delay element 12, translates trigger 13 into state O.

In order to quantify by the number of events in the initial state, register 3 records the value of the numbers that, upon receipt of which, you can make an assumption about the nature of the process, in-registers 6 are the boundaries of time intervals in which, by assumption, this number of events can occur, counters 1, 5, 9, 10, and 15, and trigger 13 is set to state O.

The input 21 receives impulses at the time of occurrence of events. At input 23, a sequence of pulses is applied with a frequency that provides the required to4HocTb counting of quantification intervals. Thus, in the counter 5 the value of the interval over which a predetermined number of events takes place is formed. If the value of the counter 1 is equal to the value of the register 3, the comparison circuit 2 is triggered and the enabling signal is fed to the input of the counter 10, delay element 4 and to the inputs of the group of elements AND 8. The device then works as in the case of time quantification.

To perform the functions of the prototype in the initial state, registers 6 recorded the values of the boundaries of the histogram intervals, counters 1, 5, 9, 10, and 15 are set to O.

Let random information be sent to information input 22

four

numbers, and input 24 is given a signal at the time of arrival of numbers. The device then works, as for the case of time quantification.

Q 5 0

5 o

about

five

Claims (1)

Invention Formula A device for forming a histogram by author. St. No. 1038950, characterized in that, in order to expand the functionality by quantizing the process of receiving single events in real time, it contains a counter of the number of events, an additional comparison circuit, a counter of the number of quantization intervals, a register of the value of the quantization interval, the OR element, an additional delay element, the output of which is connected to the reset inputs of the counter of the number of events and the counter of the number of quantization intervals, the counting input of which. is an additional input of the clock frequency of the device, the counting input of the event number counter is an input of the device’s events, the output of the event number counter and the information input of the device are connected respectively to the inputs of the OR element, whose output is connected to the input of the number register, the first and second information inputs comparison circuits are connected respectively to the outputs of the count of the number of quantization intervals and the register of the value of the quantization interval, and the output is Equal to the additional circuit with avneni connected to the input of the additional delay element and the clock input of the device. Compiled by E. Sechin Rediktor M. Dylyn Tehred M. Dvdyk Proofreader M. Maximinshined Order 4438/53. Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/3 Ilpt Primary-printing company, Uzhgorod, st. Project, 4