SU1247896A1 - Device for analyzing distributions of random processes - Google Patents

Abstract

The invention relates to an information-measuring technique and can be used for processing data obtained, in particular, from the output of adaptive information-measuring systems (AIIS). The purpose of the invention is the expansion of the class of analyzed signals due to the addition of € 0 0 Н «13 ;; :::, 13 B1FLOTELING signal processing, approximated by first-degree polynomials. To this end, the device for analyzing distributions of random processes, containing a memory block, a combinational adder, connected by an output to an information input of a memory block, and an input to an output of the last, are entered into first and second registers, binary comparator, T-trigger, calibration generator and a counting pulse generator, first, second. The third, fourth, fifth, sixth and seventh elements are AND, the first and second, the OR elements, the first and second elements are NOT, the delay element, the first, second and third counters, the code matching circuit. The advantages of the device consist in the fact that it creates the possibility of processing data from the output of AIIS, which approximates signals with polynomials of both zero and first degree, 1 slug. t

Description

The invention relates to information-measuring technology and can be used to process data obtained, in particular, from the output of adaptive information-measuring systems (ANIS).

The purpose of the invention is to expand the class of analyzed signals by processing signals approximated by first-degree polynomials.

In the drawing, a block diagram of a device for analyzing distributions of random processes is shown.

The device contains information input 1J input, 2 synchronization, the first 3 and second 4 registers ,. (binary comparator 5, T-flip-flop 6, generators 7 and 8, respectively, of calibration and counter pulses, elements AND 9-12, counters 13 and 14, element OR 15, elements And 16, 7, counter 18, element And 19, element OR 20 , delay element 21, memory block 22, combinational adder 23, code comparison circuit 24.

The device is working. following ob.pJ .v OM.

Dg: to determine the density of the distribution of random processes, the time the signal remains in the differential corridors between the values of adjacent samples is measured. The quench time is measured in each sampling interval in two successive cycles — measuring the duration of the sampling interval and its processing. Received at the time t | readout X. interrupts the cycle of measuring the duration of the interval dtj - tj and starts the cycles of processing the interval & t and measuring the duration of the interval Atj, to the expected RTC-read Xj.

In the measurement cycle, the total duration of the sampling interval is determined by counting the number of calibration pulses Tj

. 1 / F, - maxi module

   A / M, „„ KS (

mum of the 1 derivative of the signal under study, the width of the differentiation corridor) corresponds to the shortest possible time of the signal in lxd.

In a processing cycle in an unnatural, accelerated, time scale, the intermediate values of the signal are restored and the duration of the entire interval is discrete-15-1I

TOV X.

At.

the entire differential corridors, located between the values of the sample and X, the sampling interval Dp i-rp of the processing cycle, a packet of counting pulses is formed, the number of which is equal to the number of calibration pulses in the i-M sampling interval. Impulse AED accompanying x. , through the second input of the device, in particular, to the T-input of the T-flip-flop 6 and transfer it to the opposite state, for example, 1. The direct output of the latter opens AND 10, 11. In this case, the counter 14 is switched to the measurement cycle mode , since its summing input through the opened element 11 and 11 begins to pass pulses from the generator 7 of calibration pulses. The counter 13 is transferred to the processing cycle mode: the summing-up input is blocked by closing the element AND 9 O at the inverse output of the T-flip-flop 6, the counter 13 fixes the number N dtjF and its subtracting input and simultaneously at the first input of the first element OR 15

pass pulses of frequency F from the generator output 8 counting pulses. The Nth counting pulse will reset the counter 13, and the transfer at its inverse output will close the AND 11 element, stopping the passage to the subtracting input, as well as to the first input of the OR element 15 of the counting pulses. A stack of counting pulses for the 1st processing cycle is formed. To complete the processing cycle before the arrival of Xj,

condition F (it) - F, is the smallest possible

those/

Where

the discretization interval at is the largest possible sampling interval. The next (i + 1) -th impulse of the AED pulses the T-flip-flop 6 into the state O and the counters 13 and 14 change roles: the calibration pulses are counted by the counter 13, and the counting pulses reduce the contents of the counter 14.

The counting code Xj is fed to the first input 1 of the device and is written to the first register 3 by the AED pulse, which simultaneously rewrites from the first 3 to the second 4 register the counting code Xi

and puts it

in the counter 18, go through the element OR 20 to the input of the initial installation

3 - 1

counter 18. Read codes X; and Xj J are checked in binary comparator 5 and code comparison circuit 24 for compliance with conditions. Conformity X, X.

AT

g-1 - - 1-1

depending on their performance depending on the counting cycle mode,

Xj X |, (The signal for the time dt. Was in the Km differential corridor, K X | (dkhd) 1 from the direct output of the code comparison circuit 24 opens element I 19 to pass counting pulses to the input of the initial installation of the third counter 18. O from the inverse of the circuit 24 comparison codes for: covers elements And 16,

17, I will block by the summing up

and subtracting the inputs of the counter 18. Each of the N N counting pulses enters into it the reference code x. This code from the output of counter 18, fed to the address input of the memory block 22, polls its Kth cell. The content of this cell is incremented by 1 in the combinational adder 23 and from its output is fed to the information input of memory block 22 and is written into the same cell by a counting pulse delayed by delay element 21 by an amount equal to the sum of the set times of the reference code x. in the counter

18, collect the combination sui mator 23 and read from the block 23 of the memory card. Thus, the content of the K-th cell of the memory block 22 is increased by the number N proportional to the residence time (in this case, At |) of the signal in the K-th differential corridor.

X: Xj.,

(The signal was during the time ut; it was located in the Km (K - 1) th, ..., (K - - f) th differential corridors, t .dx / dxd). At the first output of binary comparator 5, 1 appears. which, together with 1 coming from the inverse of you,: the code of the code comparison circuit 24, opens element 17. To pass the counting pulses to the subtracting input of the counter 18. Logic O from the second output of the binary comparator 5 and from the direct output of the code comparison circuit 24. block the remaining inputs of counter 18. The first in the processing cycle, a counting pulse, passed to the subtracting input of counter 18, reduces by 1 the reference code written in it x.,. At the output of memory block 22, the Wits contents (K - 1) th

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cells that will increase by 1 in the combinational adder 23 and written to the same cell by the first counting pulse delayed by the delay element 21 5. The following counting pulses successively reduce the code x;, installed in the counter 18, thus interrogating the cells of the memory block 22 and increasing their contents by 1 by 1, the t-th counting pulse compares the output code of the counter 18 with the code X .. 1 s direct output of the code comparison circuit 24 will open the element AND 19, a. O {inverse output will close

15 elements And 16, 17. (t + 1) -th counting pulse will go to the input of the initial installation of the counter 18, set to

its reference code is x.

and increase by

1 contents of the K-th cell of the memory block 22 20. Such a polling sub-cycle corresponds to a change in the signal from M ,,

and

finding it in each of f di4) f-. The corridors are the shortest. With + 1, the polling subcycles are repeated D times and the contents of the cells from K to K - t increase by D. Thus

D N / 1 + 1 Fc & t i / lx-, A

I: - in ("... khg).

B - A / 4XD.

, ... and,

Since M, AXi / ut; them.,""

 ux; / ut,. then d b-itj / at.

Since j and j are known in advance, the number written in each cell of the t cells of the memory block 22 for the i-th processing cycle is proportional to

the residence time of the signals in each of the t differential corridors, xx-. . The operation mode of the device is similar to the previous one, in that the counter 18, which forms the code of the address of the memory block 22 in the polling sub-cycles, adds up the counting pulses to the code x installed in it. . In the poll sub-loop, the subtracting input of counter 18 is blocked,

since the element And 17 is closed O from the first output of the binary comparator 5. 1 from the second output of the last, together with 1 from the inverse output of the code comparison circuit 24, opens

element 1b for passing in the sub-cycle of polling the counting pulses to the summing input of the counter 18. Thus, the sign of the

of the signal under study in the inverse l tj.

When processing the samples transmitted in the approximation of a signal by zero-degree polynomials, dX | will be constant for sampling intervals of any length. When processing data from the output of a non-adaptive MIS, it will be constant ut; i. And, therefore, the number N.

The sampling codes and the accompanying pulses can come both from the output of the playback unit on a magnetic tape, and directly from the output of the information-measuring system (adaptive or conventional).

Claims (1)

Invention Formula A device for analyzing distributions of random processes, containing a memory block whose output group is connected respectively to a group of inputs of a combinational adder, whose output group is connected to a group of information inputs of a memory block, characterized in that, in order to expand the class of analytes by signal processing, approximated polynomials. -g of the first degree, it contains a comparator, T-flip-flop, generator of calibration pulses, from the first to the seventh elements AND, the first and second elements OR, the delay element, the generator of counting pulses, the first, second and third counters, the comparison circuit codes, the first and second registers, with the output of the first register connected to the information input of the second register, as well as to the first inputs of the comparator and the code comparison circuit, the output of the second register connected to the second input of the comparator and to the input of the initial installation of the first counter, output which is connected to the address input of the memory and the second input of comparing skhemz codes calibration pulse generator output is connected to the first inputs of the first and second elements AND, the outputs of which are connected to the summing inputs of the second and third counters, respectively, the output of the counting pulse generator is connected to the first inputs of the third and fourth elements AND, the outputs of which are connected to the subtracting inputs respectively the second and third counters and respectively the first and second inputs of the first element OR, the inverse transfer outputs of the second and third counters are connected to the second inputs of the third and fourth elements AND, the third input of the fourth element And the second input of the first element And, respectively, are combined and connected to inverse the output of the T-flip-flop, the direct output of which is connected to the third input of the third and second input of the second And elements, the output of the first OR element, is connected to the first inputs of the fifth, the sixth and seventh elements And directly, and through the delay element - to the entry control recording blog. memory, the second inputs of the fifth and sixth elements And are connected respectively to the outputs More and Less than the binary comparator, and the outputs of the fifth and sixth elements And are connected respectively to the summing and subtracting inputs of the first . the initial setup input of which is connected to the output of the second OR element, the first input of which is connected to the output of the seventh OR element, the second input of which is connected to the forward output of the code comparison circuit, the inverse output of which is connected to the third inputs of the fifth and sixth AND elements, while the input of the first register is the information input of the device, and the synchronization input of the first register is combined with the same input of the second register, the second input of the second OR element, the input of the T-flip-flop and is connected to no device sync. Compiled by E.Sechina Editor N.Gorvat hred M.KhodanychKorrektor A.) br U; 1ar. s1k1z1128 / 50 Circulation 671 ° TsSSR VNIIPI State Committee buof for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company. Uzhgorod, st. Project, 4