SU1278889A1 - Device for determining median - Google Patents

Abstract

The invention relates to specialized computer facilities by which the task of finding the median is solved. The purpose of the invention is to increase the speed of the device. For this purpose, summing and subtracting counters, an output register, are entered into the device. The device allows all sample numbers to be processed in parallel. 1 3.p. f-ly, 3 ill.

Description

The invention relates to specialized means of computing and can be used in the statistical processing of information.

The purpose of the invention is to increase the speed of the device due to the parallel analysis of the sample numbers.

Fig. 1 is a block diagram of a device for determining the median; figure 2 - structural diagram of the source numbers; FIG. 3 is a block diagram of the control unit.

A device for determining the median (Fig. O) contains a source of 1 numbers, a control block 2, a block 3 for analyzing numbers, n Comparators A, an element OR 5, a register 6 and an AND 7 element first counter 8, second counter 9 and output register 10.

The source of numbers (FIG. 2) contains n sample registers, the number register 12 and the group of elements And 13 according to the number of bits of the registers P and 12,

The control unit (cjiHr.B} contains a generator of 14 clock pulses, triggers 15-17, four delay elements 1821 and element 22,

The device works as follows

In the initial state, the direct outputs of the triggers 15-17 of the control unit 2 have a high signal level. Register 6 of block 3 of analysis of numbers, output register 10 and counters 8 and 9 are zero, sample numbers are in each of reg registers 11, and number (n + 1) / 2 is in register 12 of number.

When applying a pulse to the setup input of the trigger 15, a high signal level appears at its inverse output, arriving at the input of delay element 18, second input of And 22 element and second inputs of And 13 source of 1 numbers, With the arrival of a high signal level at second the inputs of the elements And 13 is allowed parallel passage of the numbers set in ti registers 11 sampling and register 12 numbers, the output of the source 1 number. These numbers are received respectively at the first inputs of the comparators 4 and the information input of the counter 8;

management This pulse is formed by the delay element 18 from the front of the signal from the inverse output of the trigger 15 with its delay by the time required to set the number code () / 2 at the information inputs of the counter 8, High signal level, coming from the output of the trigger 15 to the first the input element And 22, allows the passage of clock pulses from the generator 14 to the counting input of the counter (9 through the element And 22, since its third and fourth inputs contain high signal levels. At the bit output of the counter 9, an increasing bit is formed the second code of the number, coming to the second inputs of the n comparators 4 and to the inputs of the output register 10, at the input of the recording prohibition of which there is a low level signal coming from the inverse output of the trigger 16 of the control unit 2, which prohibits writing to this register 10, with one or several code combinations of sample numbers with a code combination of the number formed at the output of counter 9 on one or several outputs of compressors.

4 High levels of signals appear that are fed to the information input of register 6. This information is recorded in register 6 by the signal from control unit 2 at the moment when the clock pulse input from the generator 14 arrives at the input, since the high resolution is at its shift resolution input signal-a from the direct output of the trigger 17,

passed through the delay element 20. High levels of signals from the outputs of the comparators also arrive at the .OR element 5, at the inverse output of which at this moment appears

a low level signal that arrives at the setup input of the trigger 17. By this signal, the trigger 17 is set to the zero state. The differential from its inverse output enters the input of the delay element 21 with its delay at the output of (n + 1) periods of clock pulses From the direct output of the trigger 17 a low signal level arrives

on the fourth input element And 22, prohibiting the passage of clock pulses from the generator 14 to the output of the control unit 2, and through the element 20

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delays with a delay of its occurrence by a time equal to 1.5 periods of clock pulses and a duration of a negative pulse formed by a delay element 20 equal to ((n + 1) -1.5) the period of clock pulses required to shift the information recorded in register 6 It enters the input of the resolution of the shift of the register 6, allowing the shift of the information recorded in it. From the output of the element And 7 information goes to the subtracting input of the counter 8, reducing the number () / 2 recorded in it by each clock pulse by the number of matches at the outputs of the comparators 4. After subtracting the pushed information for n periods of the clock frequency recorded in register 6 of recorded in the counter 8, at the output of the delay element 21, in which a delay of (n + 1) periods of clock pulses takes place, a reset pulse is input to the reset input of trigger I7, setting it to its initial state. The high signal level from the direct output of the trigger 17 through the delay element 20 enters the input of the shift register 6, prohibits the shift mode and sets the recording mode to the register 6, and the And 22 element on the fourth input, allowing the passage of clock pulses to the counting input of the counter 9, which continues to increment the digit code of a number until it next matches the code combination of one or more sample numbers. Thus, the device progresses as in the manner described above, and this mode of operation of the device continues until the output of the counter 8 does not show an impulse to zero its contents. The occurrence of a zero pulse at the output of the counter 8 indicates that the comparison operation (n + 1) / 2 numbers from the sample and the end of the function of the analysis of numbers has passed; therefore, the discharge code of the median number has formed at the output of the counter 9.

The zeroing pulse from the output of the counter 8 arrives at the first input of the trigger 16, setting it to the zero state. From the direct output of the trigger 16, the low level of the signal arrives at the third input of the And 22 element, prohibiting the passage of clock pulses through the And 22 element to the counter 9. C

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inverse trigger output 16, a high signal level arrives at the prohibition input of the output register 10, allowing the code of the median number r from the bit outputs of the meter 9 to be written to the output register 10 on the clock edge of the clock input to the recording enable input from the generator 14. From the register outputs 10 reads 0s the median value of the number. From the inverted trigger output 16, a high signal level arrives at a delay element 19, where it is delayed by 2 periods of clock pulses. Element 19 delay forms a reset signal for triggers 15 and 16 of counters 8 and 9 and registers 6 and 10. After that, the device is ready for the next processing of a sample of numbers.

Claims (2)

Invention Formula A median device containing a source of numbers, a block 5 control, a number analysis unit consisting of a first comparator, a register and an AND element, the first output of the control unit is connected to the input of issuing source numbers 0 numbers, the output of the code of the first number of the group of which is connected to the first input of the first comparator, the second output of the control unit is connected to the first input of the element AND of the block of chi analysis, characterized in that, in order to improve speed, the first and second counters and output register, and in the block of the analysis of numbers introduce the elements 0 OR and (p-1) (n is an odd number of numbers in the sample) of comparators, the control unit contains a clock pulse generator, three triggers, four delay elements and an AND element, input 5, the installation of the first trigger of the control unit is the device start input, the inverse output of the first trigger is connected to the first input of the control unit AND via 0 the first delay element is with the write enable input of the first counter and is the first output of the control unit, the output of the element And of which is connected to the counting input of the second counter, the inverse output of the second trigger is connected to the input of the write inhibit of the output register and through the second delay element with the inputs reset the first and second triggers. the first and second counters, the output register and the register, the output of the clock pulse generator is connected to the second input of the control unit AND j with the write enable entries of the output register and the register and is the second output of the control unit; the third output of the third trigger is connected to the third input of the element And the control unit and through the third delay element - with the register shift enable input, the output of the OR element is connected to the installation input into the unit of the third trigger, the inverse output of which through the fourth element The relay is connected to its reset input of the second trigger, the direct output of which is connected to the fourth input of the control unit AND, the output codes from the 2nd to the fifth numbers of the number source group are connected to the first inputs of the corresponding comparators, the output of the number source number register is connected with the information input of the first counter, separate outputs of the second counter; are connected respectively to the second inputs of all comparators and to the information input of the output register, the output of which is the device output, the outputs of the comparators are connected to the corresponding inputs of the OR element and to the information inputs of the register respectively, the output of the register is connected to the second input of the AND number analysis unit, the output which is connected to the counting input of the first counter. 2. The device according to claim 1, characterized in that the source of numbers contains n sample registers, a register of numbers and (n + l) groups of EL, and the first inputs of the elements AND of each of the n groups are connected to output fi: bits of the same name the sampling registers, the first inputs of the And (n + 1) -th group elements are connected to the outputs of the corresponding register bits of the number, the second inputs of the And elements of all groups are the resolution of issuing source numbers, the outputs of the And elements of all groups are a group of code outputs ( +1) source numbers. / Y2. /