SU1522189A1 - Device for information input - Google Patents

Abstract

The invention relates to computing and can be used as a device for automatically inputting sonar signals into a computer. The aim of the invention is to increase the reliability of the input information. The device contains an amplifier 1, an envelope selection block 2, an ADC 3, an external trigger generator 4, a buffer storage 5, a digital averaging block 6, a threshold analysis block 7, a dial register 8, a second counter 9, a second decoder 10, a second coincidence element 11, a block 12 switches, request generation unit 13, third counter 14, third decoder 15, third match element 16, clock generator 17, first counter 18, first decoder 19, AND element 20, trigger 21, first match element 22. The signal under study is fed to the input of amplifier 1. After processing in block 2, the envelope selection is last fed to the input of ADC 3. Processing of samples to detect outliers (bursts) is performed in block 6 of digital averaging and in block 7 of threshold analysis. The threshold is set in digital form on the dial register 8. Samples for the analysis time. The threshold is set in digital form on the dial register 8. Samples for the analysis time are recorded in the buffer store 5. The number of averaged samples is set in the block of 12 switches. The third counter 14, the third decoder 15, the third coincidence element 16 determine the duration of the "Request Enable" signal when issuing samples from the buffer accumulator 5 to the computer 23. 2 Il.

Description

The invention relates to computing technology and can be used as a device for automatically introducing sonar signals into a computer.

The aim of the invention is to increase the reliability of the input information.

Figure 1 shows the structural diagram of the proposed device; FIG. 2 is a block diagram of a threshold analysis block.

The device contains an amplifier 1, an envelope extraction block 2, an analogue analog digital converter (A / D converter) 3, an external trigger generator A, a buffer store 5, a digital unit 6, averaged Neii, a threshold analysis block 7, a register 8s second counter 9, a second decoder 10 , the second element 11 matches, the block 12 of switches, the block 13 forming the request, the third counter 14, the third decoder 15e tert-sh coincidence element 16, the generator 17 clock pulses, the first counter 1B5 first decoder 19 element I 20, trigger 21, first element 22 match. The device is connected to the computer 23.

The device works as follows.

The signal under study is fed to the input of amplifier 1. After processing the signal in block 2 of the envelope selection, the signal envelope is fed to the input of ADC 3, where it is sampled at a frequency determined by external trigger generator 4. The readings from the information outputs of the ADC 3 by the parallel code are simultaneously recorded in buffer buffer 5, block 6 of digital averaging and block 7 of the threshold analysis. The readings are accompanied by the Data readiness signal from the control output of the A / D converter 3 also arriving at the ready input of the query generation unit 13.

Buffer drive 5 It is a register-type storage device of the store type, which operates the first input - the first output. The size of the registers corresponds to the size of the ADC 3, and their number is equal to the maximum number of averaged samples.

Depending on the number of averaged tcounts, the number of which is chosen equal to 2, where n 1,2,3,4

0

five

0

five

0

five

0

five

and is set by the operator in block 12 of the switches, taking into account the nature of both the signal and the interference, the next count from the output of ACCH1 3 is entered into the register, the number of which is determined by the formula: K f Nm, where K is the register number, N 2 is the maximum number of registers ; m is the number of averaged samples. The input register select signal issues-- with a block of 12 switches to the inputs of the selection of the buffer accumulator 5. Thus, with the maximum number of registers of the buffer accumulator 5 equal to 16, the number of averaged samples equal to 4, the entry will be made in the 12th register. The samples as they arrive at the buffer storage by the parallel code are synchronously shifted in the direction of the older ones by the number of the registers of the accumulator.

The digital averaging unit 6 is the accumulating sum — a torus, the contents of the output register of which can be shifted from in the direction of the lower bits, which allows dividing the sum by the number of terms.

In the threshold analysis block (Fig. 2), the next sample from the ADC output is compared with the digital threshold 8 set on the dial register, and if the threshold is equal or exceeding the averaging resolution, the output signal of the block 7 is formed and the signal arrives at the block 6 resolution enable input digital averaging, which produces the summation of this and subsequent (2 -) samples. The counting of counted counts is made on the second counter 9, to the counting input of which pulses are received Data readiness from the A / D converter 3, the control input of the counter 9 is given a signal Averaging resolution from block 7 of the threshold analysis. The end of the summation is determined by the second element 11 ow.

fall

in which it is equalized.

The state of the second counter 9, decrypted by the second decoder 10, and a code corresponding to a predetermined number of samples from the switch block 12. When they coincide, the second counter 9 is reset and is set to 1 flip-flop 21, thereby allowing the passage of pulses from the generator 17 clock pulses four

cut element And 20 into block 6 of digital averaging, which at the end of the summing shift to the lower bits by

15

ten

bits n log ,, which corresponds to dividing the sum by m. The second counter is reset by a signal — from the second element 1 1. coincidence.

The number of shifts is calculated by the first counter 18, to the counting input of which pulses from the clock generator 17 are sent. The control input to the first counter 18 receives a signal from trigger 15 21. The state of the first counter 18, decoded by the first decoder 19, is compared on the first element 22, the coincidence with the code from the switch block 12 and, if they coincide, a signal is formed End of Averaging and the trigger 21 is reset, the first counter 18 and the signal is removed Averaging resolution

The design is decrypted by the third decoder 15 and compared on the third element 16, the match with the code from the switch block 12. When they coincide, the end of exchange signal is generated, resetting the request resolution and nulling the third counter 14.

Block 7 threshold analysis contains a block 24 elements 2I-OR-NOT element OR 25, input register 26, the first delay element 27, the adder 28, the second delay element 29, the first element And 30, the second element And 31, the first trigger 32, the second trigger 33, the third element nt 34 delay (see Fig.2).

Block 7 works as follows. The next ADC counting 3, followed by the ADC Ready signal, or the next averaged value, followed by the End Averaging signal, after inverting g, the block 24 of elements 2I-2OR-NOT is entered; reverse code in the input register 26 on the signal from the element OR 25, 20

25

held on delay element 34. An adder 28 produces a total block 7 threshold analysis. The obtained averaged value is obtained from the information output of digital averaging unit 6 to the second information input of the unit 7 of the threshold analysis. Synchronization of the reception of the DOSING of the contents of the input register 26 with the digital threshold coming from the dial register 8. If the analyzed sample or the averaged value more than npi is equal to the threshold, then 35 the result of the sum is negative, i.e. the sign bit of the adder 28 is set to 1. In this case, the first or second flip-flop 32 and 33 are set to 1. The flip-flop 40 is selected by the ADC ready signal or the end of averaging delayed by delay element 27 or 29. The delay of these signals is performed at the time of installation 45 of the input register 26 and execution

summation .. Trigger reset 32 Diluted by the End Averaging signal, which enters the averaging input of the threshold analysis block 7, which compares the averaged value with the digital threshold set on the dial register 8 and in case of equality or exceeding the resolution of the block 7 request for g - a horn analysis at the input of the request resolution of the request generation unit 13; a signal is issued;

Ca, the duration of which corresponds to the number of 5 counts averaged and being in the buffer storage device. The data readiness signal to the attendant of the next ADC 3 counts is calculated, and the data from the buffer accumulator 5 is computed in the computer and simultaneously the next ADC 3 read samples are recorded. The duration of the request permission signal is determined by the third counter 14 which receives signals from the ADC 3, the resolution in the account, t is determined by the presence of a signal. The resolution of the request. Each count is accompanied by an increase of the content of the third counter by 14 units. It consists of a query / scrap solution. The end of the third element exchange.

fulfilled by cna-shaped

16 matches.

50 Reset trigger 33 Averaging resolution; produced by the End Averaging signal generated by the first element 22 of the match.

In practical situations, for example, when processing sonar signals containing individual outliers (bursts), the device not only allows you to automatically enter the analyzed signals,

15 5221896

The design is decrypted by the third decoder 15 and compared on the third element 16, the match with the code from the switch block 12. When they coincide, the end of exchange signal is generated, resetting the request resolution and nulling the third counter 14.

Block 7 threshold analysis contains a block 24 elements 2I-OR-NOT element OR 25, input register 26, the first delay element 27, the adder 28, the second delay element 29, the first element And 30, the second element And 31, the first trigger 32, the second trigger 33, the third element nt 34 delay (see Fig.2).

Block 7 works as follows. The next ADC counting 3, followed by the ADC Ready signal, or the next averaged value, followed by the End Averaging signal, after inverting g, the block 24 of elements 2I-2OR-NOT is entered; reverse code in the input register 26 on the signal from the element OR 25, 20

25

held on delay element 34. Totalizer 28 is produced

query solution / scrap End of the exchange of the third element

fulfilled by cna-shaped

16 matches.

0 Reset trigger 33 Averaging resolution; produced by the End Averaging signal, formed by the first element 22 of the match.

In practical situations, for example, in the processing of hydroacoustic signals containing individual outliers (bursts), the device not only allows you to automatically enter the analyzed signals, eliminating impulse noise counts, but also makes it possible to lower the detection threshold of the useful signal without reducing the likelihood false alarm, which cannot be done with the help of well-known input devices.

Claims (1)

Invention Formula A device for information input, containing an amplifier, an envelope selection unit, an analog-digital converter, an external start generator, a clock pulse generator, the first and second counters, the first and second decoders, the query generation unit and the buffer storage, and the input amplifier is the input of the device, the output of the amplifier is connected to the input of the block of the allocation, the output of the external start generator is connected to the input and input analog-digital converter. The information outputs and data availability output of which are connected respectively to the information inputs of the buffer accumulator and the data readiness input input of the request generator unit, the outputs of the buffer accumulator and the output of the request generator unit are respectively the device’s information and control outputs, the output of the clock generator is connected the counting input of the first counter, the outputs of which are connected to the inputs of the first decoder, the outputs of the second counter connected to the inputs of the second decoder, о т And, in order to increase the reliability of the input information, a digital averaging block, a threshold analysis block, a register, a third counter, a third decoder, first, second and third match elements, an And element, a trigger and a switch block, an output of the allocation unit are entered into the device. the envelope is connected to the information input of the analog-digital converter, whose information outputs are connected to the information inputs of the digital averaging unit and the first information inputs of the threshold analysis block, the data availability flow of the analog-digital converter unit is connected to the data availability input of the digital averaging unit, the data availability input of the threshold analysis unit, the clock input of the buffer accumulator and the QO counting inputs of the second and third counters, the output of the resolution resolution of the threshold analysis unit is connected with the block request enable input and with the control input of the third counter, the output of the clock generator is connected to the first input of the element I, the second input of which is connected to the forward output of the trigger and with the control input of the first counter, the reset input of which is connected to the output of the first coincidence element, the trigger reset input and the averaging end input of the threshold analysis block, the outputs of the first decoder are connected to the first inputs of the first coincidence element, the second inputs of which are connected to the switch block outputs, with the inputs of the buffer storage sample and with the first inputs of the second and third match elements, the outputs of the second decoder are connected to the second inputs of the second match element, the output of which o is connected to the trigger setup input and to the reset input of the second counter, the register outputs are connected to the third information inputs of the threshold analysis block, the exchange end input of which is connected to the reset input of the third counter and to the output of the third match element, the second inputs of which are connected to the third decoder outputs, the inputs of which are connected to the outputs of the third counter, the information output of the digital averaging block is connected to the second information input of the threshold analysis block, the input of the resolution averaging digital-block .go median - connected to the output - resolution median threshold analysis unit and a control input of the second counter, and elemeyta output connected to a clock input tsif- block rovogo median. dzig.2