SU1661827A1 - Speech sounds recognition device - Google Patents

Abstract

The invention relates to a technique for analyzing and recognizing speech signals and can be used in automated control systems for industrial objects and for data input into computers. The device for recognizing speech sounds comprises a microphone 1, an amplifier 2, an analog-to-digital converter 3, a memory unit 5, an indication unit 11 and a control unit 12. The purpose of the invention is to reduce hardware costs. For this purpose, multiplexer 4, code converter 6, and modulo 2 adder 7, the element OR 10, the first and second registers 8, 9, and the converter 6, multiplexer 4, the element OR 10, and registers 8, 9 are entered in the device in series. connected to the control unit 12. 2 Il.

Description

The invention relates to techniques for the analysis and recognition of speech signals and can be used in automated systems for controlling industrial facilities and entering data into a computer.

The aim of the invention is to simplify.

In FIG. 1 shows a block diagram of a device.

The device comprises a microphone 1, amplifier 2, analog-to-digital converter 3, multiplexer 4, memory unit 5, code converter 6, modulo adder 7, first register 8, second register 9, OR element 10, indication block 11, control unit 12 .

Block 12 contains a threshold element 13, a first trigger 14, a pulse generator 15, a frequency divider 16, a first counter 17, a first element And 18, a second counter 19, a one-shot 20, a third counter 21, a second trigger 22, a second And 23 element, a third element And 24, counter 25 addresses, inverter 26, the fourth element And 27.

In FIG. 2 is a timing diagram of the operation of the device, where a is the output of the first trigger 14.6 is the output of the first counter 17, b is the output of the first element And 18, d is the output of the second trigger 22, d is the output of the third element And 24, e is the output of the OR element 10, g - the output of the second element And 23.

A device for recognizing speech sounds comprises a microphone 1, an amplifier 2, and an analog-to-digital converter 3, the outputs of which are connected to the first information inputs of the multiplexer 4. The second information inputs of the latter are connected to the outputs of the memory unit 5, implemented on standard programmable memory microcircuits. The multiplexer 4 is intended for switching signals from the outputs of the converter 3 or the memory unit 5 to the inputs of the code converter 6, designed to convert the parallel code to serial and executed on a shift register, the bit capacity of which matches the bit of the converter 3. The output of the code converter 6 is connected to the first input of the adder 7 modulo two, the remaining inputs of which are connected to the corresponding outputs of the first register 8. The information input of the sequential recording of register 8 is connected to course of the adder 7, and the outputs of the first register 8 connected to the inputs of a second register 9 and the OR gate 10. The outputs of the second register 9 are connected to parallel data inputs of the first register recording SL

The adder 7 modulo two and the first register are designed to form a code combination, which is a compressed output from the Converter 6 code. The width of the first register 8 is equal to the capacity of the Converter

3. The connection of the outputs of the first register 8 to the adder 7 is determined by a polynomial defining an information compression algorithm. So, for example, for a 16-bit register. 8 with a polynomial of information compression X ¹⁶ + x ¹² + X ⁹ + X ⁷ to the adder 7 modulo two connected respectively the 16th, 12th, 9th and 7th outputs of the first register 8. The second register is designed to store the code the combination obtained in the first register 8, as a result of compression of information received through the Converter 6 and the multiplexer 4 from the Converter 3.

The corresponding inputs and outputs of amplifier 2, converter 3, multiplexer 4, code converter 6, first 8 and second 9 registers, memory unit 5, OR element 10 and indication unit 11 are connected to the control unit 12. The output of the amplifier 2 is connected to the threshold element 13 of the unit 12. The threshold element 13 determines the beginning of the recognition cycle of speech sounds.

The capacity of the first 17 and second 19 counters of the control unit 12 is determined by the capacity of the converter 3. In this case, the capacity of the first counter 17 is equal to the number of clock cycles (t) during which the maximum value of the analog signal is converted to code, and the second counter 19 is log ₂ n, where η - bit capacity of the Converter 3.

The first counter 17 of the control unit 12 is designed to determine the end of the conversion of the analog signal to a code on each quantization cycle of the analog signal supplied to the converter 3. The second counter 19 is used to determine the end of the conversion of the parallel code to serial converter 6. The third counter 21 is used to determine the end of processing input analog signal and allows you to start analysis of the information received in order to recognize it.

The device operates as follows.

The speech signal received by the microphone 1 and amplified by the amplifier 2, enters the control unit 12, where it is analyzed by the threshold element 13. Moreover, if the signal is greater than the response value of the element 13, the first trigger 14 is set to a single state (Fig. 2a) and starts the generator 15 pulses, the signals from which enter the frequency divider 16. The divider 16 generates signals of two frequencies. In this case, the signals from the first output of the divider 16 should have a frequency η times greater than the signals from the second output of the frequency former. Since the first counter 17 during initial installation is set to a value other than zero, the pulses from the first output of the divider 16 are blocked by the first element And 18, and the pulses from the second output of the divider 16 are fed simultaneously to the converter 3 and the first counter 17. In this case, the converter 3, the code corresponding to the analog signal is generated, and the first counter 17, operating in the subtraction mode, generates a signal that determines the duration of the conversion of the analog signal of the maximum value for this converter I 3.

Since during the initial installation, the second trigger 22 is set to zero, the outputs of the multiplexer 4 are connected to its first information inputs. When a signal of a single value appears from the output of the first counter 17 (Fig. 2 b), indicating its zeroing, the values generated by the converter 3 of the code are recorded in the converter 6.

At the same time, this signal from the output of the first counter 17 allows the passage of pulses from the first output of the frequency divider, through the first element And 18 (Fig. 2 c) to the clock inputs of the generator 6 and the second counter 19. In the converter 6 and register 8, information is shifted at each clock , which is summed appropriately on the adder 7 modulo two and enters again into the first shift register 8. At the same time in the second counter 19, the clock pulses are counted, which are necessary for converting the parallel code to n Consequently converter 6. When the counter 19 overflows generated signal which passes through the monostable multivibrator 20 to the first counter 17, it sets an initial value other than zero. At the same time, at the output of the first counter, the signal changes the value from unity to zero, thereby prohibiting the passage of pulses through the first element And 18. Upon receipt of the next pulses from the second output of the frequency divider 16, the device operates as described above, with each signal from the output of the first counter 17, the value of the third counter 21 decreases, and the parallel information from the converter 3 is converted by the converter 6 into a serial one and is compressed in accordance with that implemented on the adder 7 and the first tre 8 polynomial division. When zeroing the third counter 21, which corresponds to the end ^{1 of the} conversion of the input speech signal, the second trigger 22 is set to a single state (Fig. 2 g). In this case, the outputs of the multiplexer 4 are connected to the output of the memory unit 5, and the contents of the first register 8 are written in parallel to the second register 9, which indicates the completion of the code generation by the transducer 6, the adder 7 modulo 2 and the first register 8, which represents compressed information about the recognized speech signal .

We prove the ability to recognize audio signals in the device.

In general, if register 8 consists of η bits, and the binary input sequence has a length of I big, then we can say that in the device 2 ¹ possible input signals are displayed in 2 ^P variants of the codes of register 8, i.e. each variant of register code 8 can correspond to 2 ¹ ' ⁿ input binary sequences. Then the probability of ambiguous correspondence of a certain sound signal is determined by I ^- η _.

and the probability of a unique match

I - ^η _ ί

Po = 1 - Pn.o = 1 - --- ~,

- 1

When the number tends to infinity, the second term Po tends to 2Ί, therefore, in the case of a 16-bit register, the probability that each input sound signal uniquely corresponds to a 16-bit code Po = 1-2 ¹⁶ = 0.999998. Thus, high reliability of recognition of audio signals is achieved.

After setting the trigger 22 to a single state, the analysis of the code generated in the first register 8 begins in order to recognize it. To do this, the first register 8 receives information from the memory unit 5, which represents a code that, when summed modulo two by a signature corresponding to a specific recognizable sound signal, generates a zero value code in the first register 8.

If the code in the first register 8 is different from zero, the unit signal from the output of the element AND 10 (Fig. 2 e) is fed to the input of the second element And 23 (Fig. 2 g), the output of which also sets the unit level, which allows the passage through the third element And 24 pulses from the output of the counter 17 to the counting input of the counter 25 addresses. At the first address set as a result of the output of the counter 25, a parallel code is selected from the memory unit 5, recorded in the memory unit in advance. At the same time, the signal from the output of the counter 17 allows the passage of pulses from the first output of the frequency divider 16 through the first element 18 to the clock inputs of the code converter 6, the first register 8 and the second counter 19. In the converter 6 and register 8, the information selected by the first address from the memory unit 5, which is summed appropriately on the adder 7 modulo two with the code generated earlier in the register 8. Simultaneously, in the second counter 19, clock pulses are counted, which are necessary we convert the parallel code to serial by the converter 6 .. When the counter 19 is overflowed, a signal is formed which, passing through the one-shot 20 to the first counter 17, sets it to an initial value other than zero. At the same time, at the output of the first counter 17, the signal changes the value from unity to zero, thereby prohibiting the passage of pulses through the first element And 18.

Upon receipt of the following pulses from the second output of the frequency divider 16, the device operates as described above, while for each signal from the output of the first counter 17, when the register code 8 is not equal to zero, the counter counter 25 increases by one and the code value is overwritten from the second register 9 to the first register 8 for further recognition.

In the case when a zero value code is received in the first register 8, a zero level signal appears at the output of the OR element 10, indicating that recognition has occurred, which, entering the second input of the And 23 element and the input of the inverter 26, generates a zero state at the output the second element And 23 and one at the output of the fourth element And 27, which causes the trigger 14 to be set to zero, the generator 15 stops, the pulses from the output of the counter 17 pass through the And 24 element, and the contents of the address counter 25 are recorded in the block Ocean 11 indications. Block 11 decrypts the address and provides an appropriate indication.

Thus, the device allows the recognition of speech sounds with significantly lower hardware costs compared with known devices.

Claims (1)

Claim A device for recognizing speech sounds, comprising a microphone, amplifier and analog-to-digital converter in series, as well as a multiplexer, two registers and a control unit, characterized in that, for simplicity, an OR element is introduced into it, series-connected code converter and adder modulo two the output of which is connected to the information input of the sequential recording of the first register, the outputs of which are connected to the corresponding inputs of the adder modulo two, the OR element and the second register, in the passages of which are connected to the information inputs of the parallel recording of the first register, interconnected by information inputs the display unit and the memory unit, the outputs of which are connected to the second information inputs of the multiplexer, the first information inputs of which are connected to the corresponding outputs of the analog-digital converter, the outputs - to the information inputs of the code converter, and the control unit is made in the form of a threshold element, the input of which is connected to the output of the amplifier, address counter, group of outputs which is connected to the corresponding inputs of the memory block, two triggers, four AND elements, a NOT element, a frequency divider, a pulse generator connected between the output of the first trigger and the input of the frequency divider, three counters and a single vibrator connected between the output of the second counter and the control input of the recording of the first counter , while one output of the frequency divider is connected to the clock input of the first counter and the control input of the analog-to-digital converter, the other output through the first element And with clock inputs A horn counter, a first register and a code converter, the control input of which is connected to the output of the first counter, the clock input of the third counter, another input of the first AND element and through the third element And to the clock input of the address counter and the control input of the first register, the output of the third counter is connected to the input installation of the second trigger, the output of which is connected to the control inputs of the multiplexer and the second register, through the second element And to another input of the third element And and through the fourth element And to the control input row block entry indicating and resetting the first flip-flop whose setting input connected to the output po- 5 stratum element and OR element output coupled to another input of the second AND gate and via the NOT element to another input of the fourth element I.