SU1550559A2 - Device for time compression of input signal - Google Patents

Abstract

The invention relates to automation and computing, is intended to match the input signal bandwidth with the bandwidth of the analyzing and measuring equipment and is an improvement of the known device according to the author. N 888165. The invention allows, by automatically switching the measurement limits, to shorten the search time for the required measurement limit and thereby increase the speed of the device. The device contains an analog-to-code converter 1, a random access memory unit 2, a code-analog converter 3, an input signal period detection unit 4, a frequency multiplication unit 5, an addressing unit 6, a control unit 7, an automatic measurement limit selection node 8 containing analog switches 9 , 10, unit 11 of comparison elements, unit 12 of settings, units 13 and 14 of elements EXCLUSIVE OR, digital comparator 15, register 16, element 17, trigger 18, encoder 19, unit 20 amplifiers. 1 hp f-ly, 4 ill.

Description

UNION OF SOVIET SOCIALIST REPUBLINS. ₁₉ > SU „.> 1550559 A 2 (5 ¹ ) 5 G 08 C 19/00, 15/06,

STATE NOMINATION

BY INVENTIONS AND DISCLOSURES

AT GNST USSR

DESCRIPTION OF THE INVENTION

TO AUTHOR'S CERTIFICATE

888165

4319673 / 24-24

10/19/87

03/15/90. Bull. Number 10

All-Union Scientific Research (61) (21) (22) (46) (71) Tel Aviv Institute of Electrical Measuring Instruments (72) G.G. Zhivilov (53) 621.398 (088.8) (56) USSR Copyright Certificate No. 888165, class . G 08 C 19/00, 1978.

(54) TEMPORARY COMPRESSION DEVICE

INPUT SIGNAL (57) The invention relates to automation and computer engineering, pre 'assigned to match the band <of the input signal with the analyzing and measuring bandwidth

autos No. 888165. The invention allows, due to automatic switching of the measurement limits, to reduce the search time for the required measurement limit and thereby improve the speed of the device. The device comprises a converter 1 analog code, random access memory 2, converter 3 analog code, block 4 determine the period of the input signal, block 5 frequency multiplication, block 6 hell. solutions, control unit 7, node 8 for automatic selection of the measurement limit, containing analog switches 9, 10, block 11 comparison elements, block 12 settings, blocks 13 and 14 of the elements EXCLUSIVE OR, digital comparator 15, register 16, ele. cop I 17, trigger 18, decoder>

SU _I1) 1550559 • This invention relates to automatic and ke • computing and _t pre- assigned for matching of the input signal with a bandwidth of the analyzing and measuring apparatus.

The purpose of the invention is to increase the speed of the device.

I Fig. 1 is a block diagram of the proposed device; Fig. 2 [address block diagram; Fig. 3 diagram of the control unit; figure 4 timing diagrams of the operation of blocks 4, 5, 7 of the device.

The device (Fig. 1) contains an analog-code converter 1, random access memory unit 2, an analog code converter 3, an input signal period determination unit 4, • a frequency multiplication unit 5, an addressing unit 6, a control unit 7, an automatic selection unit 8 ' measurement limit, including the first 9 and second 10 analog switches, block 11 of the comparison elements, block 12 settings, the first and second blocks 13 and 14 of the elements EXCLUSIVE OR, digital comparator 15, register 16, element And 17, trigger 18, encoder 19 and block 20 • amplifiers ..

The addressing unit 6 (FIG. 2) contains a comparison element 21, a register 22, OR elements 23 and 24, AND elements 25 and 26, an inverter 27, triggers 27 and 28 with a counting input, a pulse shaper 30 and a counter 31.

The control unit 7 (FIG. 3) comprises a pulse shaper 32, a trigger 33, elements 34 and 35, a clock generator 36, element 37, triggers 38-40, elements 41 and 42, a pulse shaper 43, element 44 and pulse shaper 45.

A device for temporary compression of the input signal (figure 1) works as follows.

After starting and resetting all of its blocks, the outputs of the frequency multiplication unit 5 are locked by the signals of the control unit 7. From the sixth output of the control unit 7, clock pulses do not arrive at the frequency divider of unit 5, and the inhibitory potential from the fourth output of the control unit 7 is fed to the second input of the unit 5. The signal from the trigger 18 block 14 elements EXCLUSIVE OR is set so that its signals open all the keys of the first analog switch 9 and the inputs of the amplifiers in the block 20 of the amplifiers the input signal. The number of amplifiers in the block 20 of amplifiers is equal to the number of measurement limits of the device. Amplifiers differ from each other in gain. The outputs of the amplifiers are connected to the inputs of the second analog switch 10 and the block 11 of the comparison elements. In general, part of the amplifiers is overloaded from the influence of the input signal (an overload restriction signal is generated at their output, which is larger than the nominal signal at the corresponding limit) ₃ and some of the amplifiers are not overloaded. Of the non-loaded amplifiers, the amplifier must work in linear mode to measure the device for temporary compression of the input signal, the gain of which differs in a smaller direction from the nearest overloaded amplifier. Amplifiers with a lower gain should not work, since 'can provide measurements only with a larger error.

The second analog switch 10 before starting the measurement code from register 16 is included on the most sensitive measurement limit. The measured signal from the output of the second analog. Govogo switch 10 is fed to the inputs of the block 4 determine the period and the Converter 1 analog code. In the period determination unit 4, the periods of the input signal are inserted and enabling signals are generated at its first and second outputs.

• After starting the device, the pulse of the beginning of the input signal period from the second output of the period determination unit 4 is supplied to the first input of the control unit 7, from the sixth output of which the clock frequency is supplied to the fourth input of the multiplication unit 5, the frequency, and from the fifth output of the unit 7 the resolution potential is applied to third input of block 5. From the first output of block 4, a pulse is applied to the first input of block 5, which is equal in duration to the period of the input signal. Block 5 generates the start frequency of the converter 1 analog-code so that for a binary frequency grid in block / 5, regardless of the frequency of the input signal, its period is divided by a number in the range of numbers from η to 2n, where η is given by binary numbers, for example 512, 1024, 2048, etc. The formation of the start frequency of the converter 1 analog-code ends with the arrival at the first, input of the frequency multiplication unit 5 and at the first, θ input of the signal control unit 7 of the end of the input signal period (beginning of the next period). From the sixth output of the control unit 7, the clock frequency in the process of generating the start frequency of the converter 1 starts the analog code to the second input of the element And 17ui synchronizes its operation in order to automatically determine the measurement limit of the device. ₂ 0 At the beginning of the measurement, register 16 is reset and a zero code is generated at its output. This code corresponds to the mode of the second analog switch 10, in which the most sensitive measurement limit is turned on. If the signal at the input of the device corresponds to the most sensitive limit, the block 11 of the comparison elements, the block 13 of 3 EXCLUSIVE OR elements and the encoder 19 form zero codes at the inputs of the register 16 and the digital comparator 15.

When the codes are equal at the inputs of the digital comparator 15, a zero signal is generated from its output, which arrives at the first input of the And 17 element, the third input of which has a resolving potential from the first output of the period determination unit 4. dd In this case, the And element 17 does not switch and does not record the code of the encoder 19 in the register 16. The code at the control input of the second analog switch 10 does not change. The most sensitive measuring range remains on. The input signal, which changes during the period, is supplied to the block 11 of the comparison elements from all the amplifiers of the block 20. To gg the second inputs of the block 11 from the block 12 of the settings are supplied with voltage equal to the saturation voltages of the amplifiers in block 20. As soon as the most sensitive amplifier or part of the amplifier The gg of the bodies in block 20 will be overloaded, the signals from the output of block 11, block 13, and encoder 19 will change. The binary number at the output of encoder 19 will increase and will unambiguously correspond to the number of the measurement limit at which the device should measure the input signal Al on the next input signal period.

As the code increases at the first input of the digital comparator 15, it generates 1 at the output, which is fed to the first input of the And 117 element. The next clock pulse from the fifth output of the control unit 7, which comes to the second input of the And '17 element, switches it. The signal from the element And 17 in the register 16 is written the code of the encoder 19, which is fed to the second input of the digital comparator 15 and to the control input of the second analog switch 10, which includes the corresponding output of the amplifier in block 20 of the amplifiers to the inputs of the converter 1 analog code and block 4 definition period. If the codes at the inputs of the digital comparator 15 are equal, the resolving potential is removed from the first input of the And 17 element and the clock frequency does not pass through the And 17 element.

The process of finding the maximum value of the measurement limit code continues throughout the specified period of the input signal. The maximum code value corresponds to the automatically detected measuring range of the device.

Each amplifier in block 20 amplifiers correspond to two elements 1ί comparison. The output signal of the amplifier is compared by them with the maximum possible amplitude of the signal at the input of the converter. 1 analog-code (with a measurement limit of the converter 1 analog-code, for example, with + 1V and - 1V). The signals from the outputs of each pair of comparison elements of block 11 are sent to block 13 to the inputs of the EXCLUSIVE OR elements, and signals from block 13 are supplied to the encoder 19, in which Johnson's position codes are converted to binary. Binary codes are recorded in register 16 and control the operation of the first and second analog switches 9 and 10. The trailing edge of the period at which the starting frequency of the converter 1 is determined by the analog code is determined by the trigger 18, which sets the EXCLUSIVE OR potential at the inputs of block 14 of the elements, at which the code from register 16 passes to the first input of the first analog switch 9. Therefore, by the end of this input signal period, switches 9 and 10 select the device measurement limit $, and in block 5 controls eniya frequency selected clock frequency 1 analogue converter startup code. The inclusion of the switch 9 increases the input resistance of the device when measuring the input signal in the next period.

At the next (second) period 'of the input signal from the fourth output of the control unit 7, an enable signal is supplied to the second input of the frequency multiplication unit 5, and from the fifth output, the inhibit potential to the third input of unit 5. In this case, from the first / output of unit 5 to the control input converter 1 analog-code triggering pulses are fed, which are also received at the fourth input of the addressing unit. The start pulses of the converter 1 analog-code form address codes in block 6, which are supplied from its output to the random-access memory. 2. The ordinate codes of the input signal are recorded in the last during the second period of the input signal. Addresses of the ordinates of the signal are generated by block 6 until the enable signal is removed at the second input of block 5 by the control unit at the end of the second period ^ 5 of the input signal. At the end of the second period of the input signal, the start of the converter 1 analog-code is stopped, and in the operational storage unit 2, the ordinates of the input signal related to one period are accumulated at this point. Then follows the process of reproducing a periodic compressed signal.

At the end of the second period of the input signal, the control unit 7 from the first output supplies the enable potential to the control input of the converter 3 analog code and from the second output of the unit 7 to the second input of the addressing unit 6 supplies the clock frequency with which read addresses are generated in the addressing unit 6. The read addresses from the addressing unit 6 are supplied to the input of the operative storage unit 2. The read clock frequency to the control unit 7 is supplied to the second input from the second output of the frequency multiplication unit 5.

Reading information in block 2 occurs without its destruction cyclically period after period. The readable ordinates of the signal are sent to the input of the converter 3 analog code, the output of which is formed by a periodic compressed signal with an approximation error depending on the number of ordinates on its period, the characteristics of which can be measured.

During the first period of the measured signal, the start frequency of the converter 1 is set to an analog code corresponding to the frequency of the input signal, which guarantees that the period of the input signal from η to 2p ordinates.

With the beginning of the second period of the measured signal, the start pulses of the analog-to-converter converter 1 are received from the first output of the addressing block 6 from the first output of the multiplication block 5. The counter 31 reads the number of pulses from the fourth input of block 6 and with each subsequent pulse generates a new address code for block 2.

In accordance with these addresses on the second period of the measured signal in block 2, the ordinates of the input signal are fixed. After resetting the entire device to the first input of block 6, there are pulses of the beginning, periods of the input signal. Starting from the second pulse, each of them corresponds to the end of the previous and the beginning of the next period of the measured signal. These pulses are fed to the first input of the And 25 element, to the second input of which the resolving potential is supplied from the And 26 element through the inverter 27. These pulses are counted by triggers 28 and 29 with a counting input and at the moment of coincidence of the units at the inputs of the And 26 element, a signal is generated at its output corresponding to the end of the second period of the measured voltage. Shaper 30 is activated from the leading edge of this signal and generates a signal to the input of the OR element 24, and the input from the element And 25 is blocked by the output from the element And 26 through the inverter 27 'and the further passage of the beginning pulses of the periods'> the measured signal to the outputs of the counted triggers 28 is stopped and 29. The pulse of the shaper 30 received at the input of the OR element 24 writes the counter code 31 to the register 22. This code 5 corresponds to the maximum number of ordinates of the input signal recorded in block 2.

After writing the code to the register 22, the comparison element 21 is triggered and, with its output signal through the OR element 23, resets the address counter 31 to zero.

Block 7 signal from the sixth output connected to the fourth input of block 5, locks the first output of the block

5, and the start frequency of block 1 no longer arrives at the fourth input of the block

6. At the same time, the selected clock frequency of the input signal compression arrives at the third input of block 6 from block 7.

the trigger signal 33 is fed to the first inputs of the elements And 34 and 35. From the output of the And 34 element, the clock frequency generated by the generator 36 is supplied to the fifth output of the control unit 7.

In block 4 for determining the period, the moments of the beginning of one period after another are determined and, from its second output, the pulses of the beginning of the periods of the measured signal are fed to the first input of block 7, and in it to the first input of element And 37, to the second input of which an enabling potential is supplied with trigger 38.

The first pulse passing through the And 37 element switches the trigger 39 to the counting input, the direct output of which is connected to the second input of the And 35 element. The inverse output of the trigger 40 is connected to the third input of the And 35 element. When switching τρκι-hera 39, the And 35 element is triggered and

Again, the counter generates 31 codes of 5 ordinates of the signal ordinates, the maximum code of which is recorded in register 22. Upon reaching counter 31 of the code recorded in register 22, all the ordinates codes written in block 2 are sequentially fed to the input of converter 3 one input period. From block 2 codes are read without destroying the information. As soon as the code of the counter 31 becomes equal to the code of the register 22, an element is triggered. 21 comparisons and resets the counter to zero. Since counting pulses continue to arrive at the input of the counter 31 from the third input of block 6, the process of outputting information from block 2 continues. Such a process occurs cyclically, period after period, until the next device startup, at which the zero code will be recorded in register 22.

• The control unit 7 operates as follows.

The Start signal from an external device (or generated by a button on the front panel of the device) is supplied to the driver 32, from the output of which a general reset signal is removed, which resets all triggers and goes to the second output of block 7. From the trailing edge of the reset signal, it works driver 32, which sets the trigger 33 with its signal. You50. sends the enable potential to the fourth output of block 7 for the time of the first period of the input signal. The resolving potential from the fourth output of block 7 is removed when the next pulse of the beginning of the period arrives at the first input of the And 37 element. This pulse resets the trigger 39 and sets the trigger 40 at the counting input, which removes the resolving potential from the third input of the And 35 element. At the same time, at the inputs of the element And 41, the resolving potentials turn out to be from the direct output of the trigger 40 and the inverse output of the trigger 39. From the output of the And 41 element, the sixth output of block 7 receives the resolution potential for the time of the second period of the measured one. signal. The resolving potential from the sixth output of block 7 is removed when a third pulse of the beginning of the period of the input signal arrives at the first input of the And 37 element, from which it will switch to 1 trigger 39. As soon as the trigger 39 is switched, the inputs of And 42 at (resolution potentials go from whose signal appears at its output, corresponding to the end of the second period of the measured signal.The output signal of the element 42 is excited by the driver 43, which sets a trigger 38 by its signal.

From the output of the trigger 38, the resolving potential is set at the pep1 1 i 2 in the output of block 7, which is supplied to the converter 3 analog code.

From the inverted output of the trigger 38, the And 37 element is locked at the second input, while the direct output of the trigger 38 receives the resolving potential at the first input of the And 44 element. From the second Income of block 7, a read frequency comes to the second input of the And 44 element, jq which, having passed the And 44 element, goes to the third output of the 7 block and is fed to the second input of the addressing block 6 to form a time-compressed signal. fifteen

Claims (2)

one (61) 888165 (21) 4319673 / 24-24 (22) 10/19/87 (46) 03/15/90. Vksh. Number 10 (71) All-Union Scientific Research Institute of Electrical Instruments (72) G.G.Zhivilov (53) 621.398 (088.8) (56) USSR Copyright Certificate No. 888165, cl. G 08 C 19/00, 1978. (54) DEVICE FOR TEMPORARY COMPRESSION INPUT SIGNAL (57) The invention relates to automation and computer technology, is intended to match the input signal band with the bandwidth of the analyzing and measuring equipment and is an improvement of the known device according to hG / auth. No. 888165. The invention allows, by automatically switching the measurement limits, to shorten the search time for the required measurement limit and thereby increase the speed of the device. The device contains an analog-to-converter 1, an on-line storage unit 2, a code-analog converter 3, an input signal period detection block 4, a frequency multiplication block 5, an addressing block 6, a control block 7, a measurement limit automatic selection node 8 containing analog switches 9 , 10, unit 11 of comparison elements, unit 12 of settings, units 13 and 14 of elements EXCLUSIVE OR, digital comparator 15, register 16, element 17, trigger 18, decoder 19, unit 20 amplifiers. 1 hp f-ly, 4 ill. about ss (L Q eight SL JV About JV with N) Fyg.1 The invention relates to automation and computing and is intended to match the input signal bandwidth with the bandwidth of the analyzing and measuring equipment. The purpose of the invention is to increase the speed of the device. Figure 1 presents the block diagram of the proposed device; Fig, 2 - ischema addressing unit; FIG. 3 is a diagram of the control unit j in FIG. 4 — timing diagrams of operation of units 4, 5, 7 of the device. i The device (Fig. 1) contains an analog-code converter 1, an on-line storage unit 2, a code-analog converter 3, an input signal period detection unit 4, a frequency multiplication unit 5, an addressing block 6, a control unit 7, an automatic measuring limit selection node 8 , including the first 9 and second 10 analog switches, block 11 of the comparison elements, block 12 of the settings of the first and second blocks 13 and 14 of the elements EXCLUSIVE OR, digital comparator 15, register 16, element 17, trigger 18, encoder 19 and block 20 of amplifiers. The addressing unit 6 (FIG. 2) contains a comparison element 21, a register 22, elements OR 23 and 24, elements AND 25 and 26, an inverter 27, triggers 27 and 28 with a counting input, pulse generator 30 and a counter 31. The control unit 7 (FIG. 3) contains a pulse shaper 32, a trigger 33, And 34 and 35 elements, a clock frequency generator 36, And 37 element triggers 38-40, And 41 and 42 elements, a pulse shaper 43, And 44 element and pulse shaper 45. A device for temporarily compressing the input signal (FIG. 1) operates as follows. After starting and resetting all its blocks, the outputs of the frequency multiplying unit 5 are locked by the signals of the control unit 7. From the sixth output of control block 7, no clock pulses arrive at the frequency divider of block 5, and the second input of block 5 is supplied with the inhibitory potential from the fourth output of control block 7, using the signal from trigger 18, block 14 of elements EXCLUSIVE OR is set 0 five 0 five 0 five 0 five 0 five that all the keys of the first analog switch 9 are opened with its signals and an input signal is supplied to the inputs of the amplifiers in the amplifier unit 20. The number of amplifiers in a block of 20 amplifiers is equal to the number of limits for measuring the device. Amplifiers differ from each other in gain. The outputs of the amplifiers are connected to the inputs of the second analog switch 10 and the unit 11 of the comparison elements. From the input signal, in the general case, some of the forces are overloaded (at their output, an overload limiting signal is generated that is larger than the nominal signal at the corresponding limit), and some of the amplifiers are not overloaded. Of the non-overloaded amplifiers, an amplifier should operate in a linear mode for measuring with a device for temporarily compressing the input signal, the gain of which is different from the nearest overloaded amplifier. Amplifiers with a lower gain should not work, as they can provide measurements only with greater error. The second analog switch 10 before starting the measurement with a register 16 is switched on to the most sensitive measurement limit. The measured signal from the output of the second analog switch 10 is fed to the inputs of the period determination unit 4 and the analog-code converter 1. In the period definition block 4, the periods of the input signal are separated and the enabling signals are generated at its first and second outputs. After starting the device, the pulse of the beginning of the input signal period from the second output of the period determining unit 4 is fed to the first input of the control unit 7, from the sixth output of which the clock frequency goes to the fourth input of the frequency multiplying unit 5, and from the fifth output of the unit 7 the resolving potential is fed to the third input of block 5. From the first output of block 4 to the first input of block 5, a pulse is applied, which is equal in duration to the period of the input signal. Block 5 generates the start frequency of the converter 1 analog-code so that when the binary frequency grid in the block / 5 regardless of the frequency of the input signal, its period is divided by a number in the interval of numbers from n to 2n, where n is given as binary numbers, for example 512, 1024, 2048, etc. The generation of the starting frequency of the converter 1 analog-code ends with the arrival at the first input block 5 multiply the frequency and the first step on the first input element And the input of the signal control unit 7 of the end of the input signal period (the beginning of the next period). From the sixth output of the control unit 7, the clock frequency in the process of shaping the startup frequency of the converter 1, the analogue code arrives at the second input of the element And 17u synchronizes its operation in order to automatically determine the measurement limit of the device. At the beginning of the measurement, register 16 is reset and a zero code is generated at its output. This code corresponds to the second analog communication mode. 20 17. The next clock pulse from the fifth output of the control unit 7, arriving at the second input of the element 17, switches it. The signal from element 17 in register 16 records the code of the encoder 19, which goes to the second input of the digital comparator 15 and to the control input of the second analog switch 10, which includes the corresponding output of the amplifier in the amplifier unit 20 to the inputs of the converter 1 analog-code and block 4 determine the period. In case of equality of codes at the entrance tator 10, at which the 25 digital comparator 15 is switched on More sensitive measurement limit. If the signal at the input of the device corresponds to the most sensitive limit, the block 11 of the comparison elements, the block 13 of the elements EXCLUSIVE OR, and the encoder 19 form at the inputs of the register 16 and the digital comparator 15 codes zero. When the codes on the inputs of the digital comparator 15 are equal, a zero signal is generated from its output, which arrives at the first input of the element 17, the third input of which is supplied with the resolving potential from the first output of the period determination unit 4. In this case, the AND element 17 does not switch and does not write the code of the encoder 19 to the register 16. The code at the control input of the second analog switch 10 does not change. The most sensitive measurement limit remains on. The input signal, changing during the period, is fed to the block 11 of the comparison elements from all the amplifiers of the block 20. Voltages equal to the saturation voltages of the amplifiers in the block 20 are supplied to the second inputs of the block 11 from the setpoint block 12. Once the most sensitive amplifier or a part of the force-gg is clocked; the clock frequency of the start of the switches in block 20 will be overloaded, forming 1 analog-code, the signals from the output of the block will be changed; trigger 18, which will be set to 11, block 13 and the encoder will 19. block 14 elements number on you During the age encoder 19, the EXCLUSIVE OR potential, at which it will and unambiguously correspond to the number of the measurement limit, at which the device must measure the input signal in the next period of the input signal. As the code increases at the first input of the digital comparator 15, it forms 1 at the output, which is 5 0 17. The next clock pulse from the fifth output of the control block 7, coming to the second input of the element And 17, switches it. The signal from element 17 in register 16 records the code of the encoder 19, which is fed to the second input of the digital comparator 15 and to the control input of the second analog switch 10, which includes the corresponding amplifier output in the amplifier block 20 to the inputs of the analog-code converter 1 and block 4 determine the period. In case of equality of codes at the inputs 0 five the input element And 17 is removed permitting potential and the clock frequency through the element And 17 does not pass. The process of finding the maximum value of the measurement limit code continues for the entire specified period of the input signal. The maximum code value corresponds to the automatically found measurement limit of the device. Two amplifiers 11 correspond to each amplifier in the amplifier unit 20. The output signal of the amplifier is compared by them with the maximum possible amplitude of the signal at the input of the converter. 1 analog-code (with the measurement limit of the converter 1 analog-code, for example, with + 1V and -1B). The signals from the outputs of each pair of elements of the comparison block 11 are fed to the block 13 to the inputs of the EXCLUSIVE OR elements, and from block 13 the signals are fed to the encoder 19, in which the Johnson position codes turn into binary ones. Binary codes are written to register 16 and control the operation of the first and second analog switches 9 and 10. The trailing edge of the pulse of the period in which the 5 0 The rum code from register 16 passes to the first input of the first anap switch 9. Therefore, by the end of this period of the input signal by switches 9 and 10, the measurement limit of the device is selected, and in frequency control block 5, the clock frequency of the converter 1 analog-code is selected. Turning on the switch 9 increases the input impedance of the device when measuring the input signal for the next period. In the next (second) period of the input signal from the fourth output of the control unit 7, the enabling signal is supplied to the second input of the frequency multiplying unit 5, and from the fifth output - the inhibitory potential to the third input of the unit 5. From the first output of the unit 5 to the control input the converter 1 analogue code is given triggering pulses, which also arrive at the fourth input of the block 6 addresses Pulses start converter 1 analog-code form in block 6, codes of addresses that are sent from its output to the operational storage unit 2. In the latter, the ordinates of the input signal are recorded during the second period of the input signal. The addresses of the ordinates of the signal are formed by block 6 until, at the second input of block 5, by block The control will not remove the enable signal at the end of the second period of the input signal. At the end of the second period of the input signal, the start of the converter 1 analog-code stops, and in the operational storage unit 2 the ordinates of the input signal related to the same period accumulate at this moment. Then the repetition of the periodic compressed signal follows. At the end of the second input signal period, the control unit 7 from the first output supplies the enabling potential to the control input of the converter 3 code analogue and from the second output of the block 7 to the second input of the addressing unit 6 supplies the clock frequency from which the read addresses are formed in the addressing unit 6. The read addresses from the addressing unit 6 are fed to the input of the operational storage unit 2. The read clock frequency to the post control unit 7 five 0 It goes to the second input from the second output of the frequency multiplying unit 5. The reading of information in block 2 occurs without its destruction, cyclically period by period. The read codes of the ordinates of the signal arrive at the input of the converter 3 of a code analog, the output of which forms a periodic compressed signal with an approximation error depending on the number of ordinates on its period, the characteristics of which can be measured. During the first period of the measured signal, the frequency of the starting of the converter 1 analog-code is set corresponding to the frequency of the input signal, which guarantees that the input signal from n to 2 n will receive the ordinates. From the beginning of the second period of the measured signal to the fourth input of the addressing unit 6, the starting output of the analog-code converter 5 from the first output of the multiplication unit 5-5. Counter 31 reads the number of pulses from the fourth input of block 6 and with each next pulse generates a new address code for block 2. In accordance with these addresses, the ordinate codes of the input signal are fixed in block 2 in the second period of the measured signal. After resetting the entire device to the first input of block 6, the pulses of the beginning of the periods of the input signal arrive. Starting with the second pulse, each of them corresponds to the end of the previous one and the beginning of the next period of the measured signal. These pulses arrive at the first input of element 25, the second input of which is supplied by the resolving potential from element 26 through the inverter 27. These pulses are counted by triggers 28 and 29 with the counting input, and at the time the units coincide at the inputs of element 26, a signal is generated at its output corresponding to the end of the second period of the measured voltage. Shaper 30 is triggered from the leading edge of this signal and generates a signal to the input of the element OR 24, and the potential of the pulses from the beginning of periods to stop through the inverter 27 blocks the input from the element AND 26 through the inverter 27. five 0 five 0 The t measured signal at the outputs of the counting triggers 28 and 29. The pulse received by the input element OR 24 of the driver 30 records the code of the counter 31 in the register 22. This code corresponds to the maximum number of the input signal recorded in block 2. After writing the code to the register 22, the comparison element 21 is triggered and by its output signal through the element OR 23 resets the address counter 31 to zero. Block 7 with a signal from the sixth output connected to the fourth input of block 5 locks the first output of the block 5, and the launch frequency of block 1 no longer goes to the fourth input of the block 6. At the same time, the third input of block 6 from block 7 receives the selected clock frequency of compression of the input signal. By the counter 31, the codes of the addresses of the ordinates of the signal, the maximum code of which is recorded in register 22, are formed again. When the counter 31 reaches the code recorded in register 22, the code-analogue is sequentially input to the converter 3, all ordinates recorded in block 2 on the same period of the input signal . From block 2, codes are read without destroying information. As soon as the counter code 31 becomes equal to the register code 22, the reference element 21 is triggered and resets the counter to zero. Since the input to the counter is 31 seconds. The third input of block 6 continues to receive counting pulses, the process of outputting information from block 2 continues. Such a process occurs cyclically, period by period, until the next launch of the device, at which zero code is written to register 22.  The control unit 7 operates as follows. A start signal from an external device (or formed by a button on the front panel of the device) is fed to the driver 32, from whose output a general reset signal is removed, which zeroes all the triggers and goes to the second output of block 7. The back of the reset signal triggers the driver 32, which your signal sets the trigger 33. You ... j,  50 35 40 "with 0 the trigger signal 33 is supplied to the first inputs of the elements 34 and 35. From the output of the element 34, the fifth output of the control unit 7 is the clock frequency generated by the generator 36. In block 4 of the period definition, the moments of the beginning of one period after another are determined, and from its second output, the pulses of the beginning of periods of the measured signal arrive at the first input of block 7, and in it at the first input of the And 37 element, to the second input of which I allow. trigger potential 38. The first pulse transmitted through the element I 37 switches the trigger 39 via the counting input, the forward output of which is connected to the second input of the element 35. The inverse output of the trigger 40 is connected to the third input of the element 35. When the switching signal 39 is switched, the element 35 also operates and. sends to the fourth output of block 7 the permissive potential for the time of the first period of the input signal. The resolving potential from the fourth output of block 7 is removed when the next pulse of the beginning of the period arrives at the first input of the element 37. This pulse resets the trigger 39 and sets the trigger 40 at the counting input, which removes the resolving potential from the third input of the element 35. At the same time, at the inputs of the element And 41 are the resolving potentials from the direct output of the trigger 40 and the inverse output of the trigger 39. From the output of the element 41, the sixth output of the block 7 arrives, allowing the potential for the time of the second period of the measured signal. The resolving potential from the sixth output of block 7 is removed when the third pulse of the beginning of the input signal period arrives at the first input of the element 37, from which it switches to 1 flip-flop 39. As soon as the flip-flop 39 switches to the inputs of the And 42 element at; the signal corresponding to the end of the second period of the measured signal appears at its output. The output signal of the AND 42 excites the driver 43, which with its signal sets the trigger 38. From the output of the trigger 38, the resolving potential is set at the first output of the block 7, which is supplied to the code-analog converter 3. From the inverse output of the trigger 38, the element 37 is locked at the second input, and the direct output of the trigger 38 to the first input of the element 44 enters the resolving potential. From the second input of block 7 to the second input of element 44, the read frequency comes, which, having passed through element 44, enters the third output of block 7 and is fed to the second input of block 6 of addressing to form a time-compressed signal. invention formula  1. A device for temporarily compressing the input signal according to the auth.St. No. 888165, characterized in that, in order to improve speed, a node for automatic selection of the measurement limit is entered into it, the first output of which is connected to the input of the input signal period detection unit and the first analog-code converter input, from the first to the fourth inputs of the automatic selection node the measurement limit is connected respectively to the input of the device, the second and fifth outputs of the control unit and the first output of the input signal period determination unit; the second output of the node for automatic selection of the measurement limit is are second output device. 2. The device according to claim 1, of which is that the node for automatic selection of the measurement limit contains analog switches, a block Amplifiers, Comparison Elements Block, Settings Block, EXCLUSIVE OR Elements Blocks, Encoder, Digital Comparator, Register, Trigger and Element And, the output of the first analog switch is connected through the amplifier block to the first input of the second analog switch and the corresponding first inputs of the comparison block, second inputs which are connected to the corresponding outputs of the block settings, the outputs of the block of comparison elements are connected to the corresponding inputs of the first block of elements EXCLUSIVE OR, the outputs of which are connected To the corresponding inputs of the encoder, the output of which is connected to the first inputs of the digital comparator and the register, the output of the register is the second output of the node and connected to the first input of the second block of EXCLUSIVE OR elements and the second inputs of the digital comparator and the second analog switch, the output of which is the first output the node, the output of the digital comparator is connected to the first input of the element I, the output of which is connected to the second input of the register, the output of the trigger is connected to the second input of the second block of elements EXCLUDING EE OR, whose output is connected to the first input of the first analog switch, the second input of which is the first input of the node, the first trigger input and the third input of the register are combined and are the second input of the node, the second input of the AND element is the third input of the node, the second input of the trigger and the third input of the AND element is combined and is the fourth input of the node. l 6SSOSSI