SU1287025A1 - Automatic meter of pulse power of microwave frequency radio signals - Google Patents

Abstract

This invention relates to radio measurements. It can be used in the systems of automatic control of electronic equipment. The aim of the invention is to extend the functionality of an automatic microwave power pulse meter for radio signals, which includes the ability to measure instantaneous values of the power of an arbitrary waveform at a given point in time. To achieve this goal, an instantaneous voltage converter 5 was introduced, a write control block 6, an address switch 15, a memory block 14, a user register 11, a quad 8, an adder 10, a split block 13, a multiplier 12, new functional connections were formed . In addition, the device contains a power divider 1, a thermal power sensor 2, an average power converter 3, a memory block 7, a switch 9, a control block 16, an indicator 17, In the description of the invention, an embodiment of blocks 6, 16 is shown. f-ly, 3 ill. e 3 (L O EO e U1

Description

The invention relates to the field of radio measurements and, in particular, can be used in systems for automatic control of electronic equipment.

The aim of the invention is to extend the functionality of an automatic microwave power pulse meter for radio signals, which consists in measuring the instantaneous values of the power of an arbitrary waveform at a given point in time.

Fig, 1 shows the structural diagram of the meter; 2 is a block diagram of the write control unit; FIG. 3 is a block diagram of the control block.

The automatic pulse power meter of microwave radio signals (Fig. 1) contains a power divider 1, a thermal power sensor 2, an average power generator 3, a detector 4, an instantaneous voltage converter 5, a recording control unit 6, a first memory block 7, a quadrant 8 , switch 9, adder 10, user register 11, multiplying unit 12, dividing unit 13 ,. the second memory block 14, the address switch 15, the control block 16, the indicator 17, the first output of the power divider 1 through the thermal power sensor 2 is connected to the input of the medium power converter 3, and the second to the input of the detector 4, the first input of the instantaneous converter 5 the voltage is connected to the detector output 4, the second input is connected to the first output of the recording control unit 6, and the output is connected to the first input of the first memory block 7, the output of which is connected to the first input of the quad 8 whose output is connected to the first input of the switch 9, the first The output of which is connected to the first input of the adder 10, and the second output to the first input of the dividing unit 13, the second input of which is connected to the output of the adder 10, and the output to the first input of the duplicating unit 12, the second input of which is connected to the output of the converter 3 average power, the third input - to the output of the second block 14chpami, and the output - to the indicator 17, the second output of the recording control block 6 is connected to the second input of the first block 7. pa,

-

287025

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Sh

20

the third output is with the first input of the second memory block 14, and the fourth output with the first input of the address switch 15, the second input of the second memory block 14 and the input of the control block 16, the first output of which is connected to the input of the address switch 15 whose third input is connected to the output of user register 11, and the output to the third input of the first memory block 7, secondly the sixth outputs of the control block 16 are connected to the control inputs of the write control block, MyjaTopa com address 15, the first memory block 7, quadrature 8 , switch 9, respectively, the eighth output to the first control input of the adder 10, the eighth output to the second control input of the adder 10, the ninth to the thirteenth outputs to the control inputs of the average power converter 3, the second memory block 14, the duplicating unit 12, the indicator - torus 17 and dividing unit 13, respectively, the input of power divider 1 is the first input of the automatic pulse power meter CBCH radio signaling, the second and third inputs of which are the second inputs of the recording control unit 6, and the control unit 16, respectively.

The recording control block 6 contains a synchrometer-driven generator 18, the first element AND 19, the pulse amplifier 20, the OR element 21, the first delay block 22, the driver of the pulses 23, the counting trigger 24, the second delay block 25, the write address counter 26, the second circuit And 27, the installation trigger 28, the third block 29 of the delay, and the output of the installation trigger 28 through the first input of the second element And is connected to the input of the counting trigger 24, the first output of which is connected to the first input of the first element And 19 and through the imaging unit 23 pulses with the first entrance element ШШ 21, the output of which is connected to the second input of the first element I 19, the output of which is connected to the input of the amplifier 20 pulses, the output of which is connected

5-5 with inputs of the first 22 and second 25 delay blocks, the write address counter 26, and is the first output of the write control block 6, the output

thirty

40

45

The second delay unit 25 is the second output of the write control block 6, the output of the first delay block 22 is connected to the second input of the OR element 21, the second output of the counting trigger 24 is connected to the first input of the installation trigger 28, the third output of the delay block 29 and is the third output of the block 6 write control, the output of the third delay block 29 is connected to the second input of the write address counter 26, the output of which is the fourth output of the write control block 6 whose input is the second input of the setup trigger 28, and v The first entrance is the second input of the second element I..

The control unit 16 comprises a reference frequency generator 30, a key 31, a pulse counter 32, a program storage unit 33, a command register 34, a command decoder 35, a decoder 36 O, a first delay unit 37, trans

the second element OR 38, the second delay 39, the program pitch counter 40, the encoder 41, the element AND 42, the second element OR 43, the counter 44, the counter 45 of the read address whose output is the first output of the control unit 16, the first input is connected to the first the output of the decoder 35 coman the first input of the register 34 commands, the first input of the counter 40 step program, the first input of the counter 32 pulses and the first input of the counter 44, and the second input connected to the second inputs of the decoder 35 commands, sweeper 44 and through the first block 37 delay - to the first input of the first element AND And 38, the output of which is the fourth output of the control unit 16, and the second input is connected to the third output of the command decoder 35, the fourth output of which under the keys to the first input of the element 42 and Fifth - Fifteenth outputs are the second, third, fifth the thirteenth outputs of the control unit 16, and the input is connected to the output of the command register 34, the second input of which is connected to the first output of the program storage unit 33, the second output of which is connected to the second input of the pulse counter 32, and the second input through the second delay block 39. Counter 40 step program and the second output member 43

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40

45

the first input of which is connected to the output of the counter, 32 pulses, the third input of which is connected to the output of the key 31, the first input of which is connected to the reference frequency generator 30, and the second input - to the output of the 36 O decoder whose input is connected to the first input block 33 program storage and exit

10 of the program step counter 40, the third input of which is connected via the encoder 41 to the output of the element I, the second input of which is connected to the output of the counter 44, whose input is

 5, the first input of the control unit 16, the second input of which is the second input of the second element 43 OR. The meter works in the following way.

The input signal is fed to a power divider 1, which directs it through two channels: an average power conversion channel including a thermal power sensor 2 and

 medium power converter 3, and signal sampling channel for level and time, including detector 4, instantaneous voltage converter 5, write control unit 6, first memory block 7, and address switch 15. On . the output of the first channel, a signal is generated that carries information from the average power of the sequence

35 input radio pulses. In the second channel, the detector 4 selects the envelope of the measured radio pulse, and by the instantaneous voltage converter 5, the instantaneous values of the envelope voltage are converted, for example, into a digital code and stored by the first memory block 7.

The device works in three. The first stage is to record the instantaneous voltage values of the envelope of the radio pulses produced by the inverter 5 of the instantaneous voltage value by quantizing it by level and time (by analog-to-digital conversion). Dp the implementation of the first stage, the control unit 16 issues control commands to

the write control block 6 and to the address switch 15, thus providing the connection of the fourth output of the write control block 6

through the switch 15 addresses to the first memory block 7.

The conversion by the inverter of the 5 m voltage value is made by the arrival of the start pulse from the first output of the recording control unit 6. In addition, the recording control unit 6 generates a write pulse to the first memory block 7 and a write address code. The entry address code comes from the write control unit 6 via the address switch 15.

Upon arrival from the control unit 16 of the control command from the second output, the installation trigger 28 is set to one position. At the same time, the passage of synchronization pulses unambiguously associated with the measured signal is allowed through the second element 27 to the counting trigger 24. After the arrival of the control command, the first synchronization pulse to the counting trigger is set to one, and the next pulse returns to zero output. . Upon transition to the initial position of the counting thruter 24, the initial trigger position 28 and the adjusting trigger 28 are thus transferred. Thus, at the output of the counting trigger 24, single ones are formed; impulse (. duration equal to the period of synchronization pulses. This impulse arriving at the first element 19 and closes the positive feedback circuit of the amplifier 20 pulses through the first line of the delay block 22 - the element 21 of the pulse 21. Formed by the driver of 23 pulses on the leading edge of the pulse from the counting A short pulse passes through the OR 21 element to the synchronized generator 18 and circulates in the ring with a period determined by the great delay of the first block 22 Zadler 11. This process continues for time of the single state of the counting trigger 24. The pulses from the output of the synchronizing generator 18 are sent as start pulses to the converter 5 of the instantaneous voltage value, these pulses, having passed the second block 25 back, the holders, are received as write pulses on the first block 7 of the memory The write address is generated by the write address counter 26 of the write control block 6 by counting pulses of a synchronous 1 r generator 18. Back of a pulse from the counting trigger 24 with a delay determined by the third delay block 29 , the write address counter 26 is reset. The non-held signal of the counting trigger 24 comes as a pulse to the second memory block 14, which also receives the code of the number n from the record address counter 26. In this way,

P -

15

ut

the starting pulse of the converter 5 instantaneous value of voltages, n write pulses and the write address code iia the first memory block 7 (T is the period

repetition of radio pulses; t is the pulse start-up period of the converter 5 of the instantaneous voltage value).

After the time required to complete the recording process,

the control unit 16 sends a command to the average power converter 3, according to which the latter converts the average power value. The result of the conversion is stored in the converter until the third stage.

The second stage of the work is the obtaining of the average power value by the disk instantaneous values of the signal envelope obtained at the first stage. At this stage, the control unit 16 sequentially generates commands for processing the information stored in the first memory unit 7.

At the beginning of this stage, the control unit 16 forms a command to the address switch 15, which switches the address busses of the first

memory unit 7 from recording control unit 6 to control unit 16, as well as a command to switch 9, which connects adder 10 to quad output 8. Next, control block 16

sequentially generates addresses

readout AND sends the Read command to the first memory block 7. Read information about the instantaneous values of the measured signal arrives

a quadrant B, where also, following a command from control unit 16, is erected in square 5 and then through switch 9 it enters, previously reset to a command from block 16, control 7.

The adder 10. The adder 10 has a memory register in its composition, which makes it possible to accumulate in it the results of the summation after reading information at each address. Summation is performed by a command from control block 16. After squaring and summing up the information read at the last address of the first memory block 7, the value stored in the adder is proportional to

And Guy, N /

where n is the number of discrete values written to the first. memory block 7, Ug is the instantaneous value of the measured signal recorded in the first memory block 7.

Upon completion of the summation, the control unit 16 sends commands to the address switch 15 and the switch 9, which respectively connect the output of user register 11 with the address bus of the first memory block 7 and the quad output 8 to the input of the splitter unit 13. The device is prepared for the final stage of operation. .

At the third (final) stage, the read command from control unit 16 reads information from the first memory block .7 at the address previously entered by the operator serving the device in the user register 11. r. The number read at this address is squared by the quad 8 and through the switch 9 enters the dividing unit 13 as a dividend. The result of the dividing unit 13

and:

B

n 2

51 and „

one-

where Uj is the instantaneous value of the voltage at the address chosen by the user,

enters the multiplication unit 12. The same unit receives the result of the average power conversion by the average power unit 3 and information from the second memory unit 14 about the number n of the instantaneous values of the input signal 287025

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recorded in the second memory block 14.

In the replicating unit 12, the commands of the control unit 16 sequentially multiply the average power values P

wed

magnitudes

AT

 Ub

and the numbers n written in

g: i: v

the first block 7 of the instantaneous value memory n of the input signal. Thus, the output value

nth

B

M

G.

chi

20

25

thirty

35

40

45

50

55

corresponds to the instantaneous value of the pulse power at the point of the time axis specified by the operator. Upon a command from the control unit 16, the measured instantaneous power value is entered into the indicator 17.

The control unit 16 operates as follows.

To start the device, the operator, using the controls, sends the Start command to the second element OR 43, which goes to the program step counter 40 and the second delay unit 39 and moves the program step counter 40 from the zero position to the first position. The binary code of the first program step generated by the program step counter 40 is inputted to the program storage unit 33, the second delayed delay unit 39 forms a read command, and the first program word is read.

The program words recorded in block 33 of storing the program sequentially consist of two parts: a time delay code and a command code issued from the control block 16 to other units of the device.

The time delay code is entered into the pulse counter 32, to the counting input of which the reference frequency is fed through the key 31 from the reference frequency generator 30. The pulses of the reference frequency are counted by a pulse counter 32, which generates an overflow signal at a time when the sum of the previously entered number and the number of pulses fed to the counter input 32 pulses exceeds the total capacity of the counter. Overflow signal through the second element OR 43

enters the counting input of the counter 40 step program. As a result, the program step counter 40 generates the address code of the next program step. The process is then repeated until the last instruction of the programs is read.

The second part of the words recorded in the program storage unit 33 is sent to the instruction register 34 as a binary instruction code, then decrypted by the decoder 35 instructions. A decoder 35 of commands directly generates control commands to all blocks of the device as potential levels of duration corresponding to the length of a program step Qii. One of the commands from the decoder 35 commands goes to the counter input of the counter 45 of the read address and through the first block 37 of the delay to the first element OR 38. At the same time, the read address counter 45 generates the binary code of the read address, and the output of the first element OR 38 forms a command to read information from the nepBoi o of the memory block 7. The read instructions thus generated are used for reading. recorded at all addresses information. In the final stage, when it is necessary to ensure reading only at one user-specified address, a different command is used from the output of the command decoder 35, which through the first CS element 38 arrives at the same read input of the first memory block 7. The formation of the information readout addresses of the first memory unit 7 is carried out in strict accordance with the number n, i.e. with the number of entries made in the first block 7 of the memory, At the counter 44, at the end of the recording step, as in the second block of the memory 14, the number of entries is recorded.

VI

memory and size calculation

"J-.I V

consists of n repeating groups of operations; in block 16 of control, the possibility of implementing cyclic repetition of groups of operations is provided;

Cycle 1-gus is performed as follows.

A special command is generated from the decoder 35 of the commands, the code of which is recorded in the program storage block 33 at the end of the array to be repeated. This command comes through AND 42, which

opened if the state of the counter 44 is not zero, and then to the encoder 41. The encoder 41 generates the binary code of the address of the command from which the repeated array starts, and writes this code into the program step counter | 40, ensuring the repetition of the process. In the process of reading, one of the commands of the decoder 35 commands, arriving at the counter 45

readout addresses also come in

to counter 44. The value of the number in the counter decreases from n to 0 as the cycles repeat. At the zero position of the counter 44, the And 42 element closes, the cyclic repetition of operations stops, the program step counter 40 goes to the next program address. Thus, to ensure the measurement process in

The program storage unit 33 should include the codes of all elementary actions for managing individual units of the device.

Claims (3)

1. Automatic impulse power meter of SBS radio signals containing a series-connected power divider with a detector connected to it, a thermal power sensor and an average power converter, a memory unit, a switch, an indicator and a control unit, and with that, with In order to expand its functionality, an instantaneous voltage value converter, a write control unit, an address switch, a second memory block, a user register, a quad, an adder, and multiplexing and duplicating blocks are entered into it, the first input of the instantaneous voltage value converter being connected to the detector's code the second input is with the first output of the write control unit, and the output is with the first input of the first memory block, the output of which is connected to the first to the entrance of the quadrator, the output of which connected to the first input of the switch, the first output of which is connected to the first input of the adder, and the second. the output to the first input of the dividing unit, the second input of which is connected to the output of the adder, and the output to the first input of the multiplying unit, the second input of which is connected to the output of the average power converter, the third input to the output of the second memory unit, and the output to the indicator the second output of the write control unit is connected to the second input of the first memory block, the third output is connected to the first input of the memory unit, and the fourth output connects to the first input of the address switch, the second input of the second memory unit and the control unit input, the first output to The second is connected to the second input of the address switch, the third output of which is connected to the output of the user register, and the output to the third input of the first memory block, the outputs from the second to the sixth control block are connected to the control inputs of the write control block, the address switch, the first memory block, quad, switch, respectively, the seventh output to the first control input of the adder, the eighth output to the second control input of the adder, outputs from the ninth to three of the tenth to the control inputs of the media converter s power, the second storage unit, a multiplier unit, an indicator, and divider block sootvets Twain input power divider is a first input of an automatic meter microwave radio pulse power, second and third inputs of which are the second inputs of the write control and the control unit block, respectively. 2. The meter in accordance with claim 1, 1, which is based on the fact that the recording control unit contains a synchronized generator, the first AND element, the pulse amplifier, element 1; SHI, the first delay unit, the driver of the pulses, the counting trigger, the second block delays, the write address counter, the second circuit And, the installation trigger, the third delay unit, the output of the installation trigger through the first input of the second element I connected to the input of the counting trigger, the first output of which is connected to the first input of the first element I and I Pulse generator with the first input of the OR element, the output of which is connected to the second input of the first element I, the output of which is connected to the input of the pulse amplifier, the output of which is connected to the inputs of the first delay unit, the second delay unit, the write address counter and is the first output of the write control unit, the output of the second delay unit ow - 0 is the second output of the write control block, the output of the first delay block is connected to the second input of the OR element, the second output of the counting trigger is connected to the first input 5 of the installation trigger, the third input, the delay block and is the third output of the write control block, the output of the third delay block is connected to the second input of the write address counter 0, the output of which is the fourth output of the write control block, the first input of which is the second input of the set trigger and the second input is the 5 second input of the second element I. 3. The meter according to claim 1 of tl and h a-. u and with the fact that the control unit contains the reference frequency generator, key, pulse counter, program storage block 0, command register, command decoder, decoder O, first delay unit, first OR element, second delay unit, program step counter , encoder, AND element, 5 second OR element, counter, read address counter, the output of which is the first output of the control unit, the first input connected to the first output of the command decoder, the first input of the command register, the first input of the program step counter first count entry pulses to the first input of the counter, and the second input is connected to the BTOpofiy input of the command decoder, to the second input of the counter and through the first delay unit to the first input of the first OR element, the output of which is the fourth output of the control unit, and the second 0 input connected to the third output of the command decoder, the fourth output of which is connected to the first input of the element I, the outputs from the fifth to the fifteenth are the second, third and 5 from the fifth to the thirteenth outputs of the control unit, and the input is connected to the output of the command register, the second input D which is connected to the first output of the program storage unit, the second output of which is connected to the second input of the pulse counter, and the second input through the second delay unit is connected to the second input of the program step counter and the output of the second OR element, the first input of which is connected to the output of the counter pulses The third input is connected to the output of the key, the first input of which is connected to the reference frequency generator, and the second input to the output of the decoder O, the input of which is connected to the first input of the program storage unit and the output of the program step counter, the third input of which is through the encoder connected to the output of the element And, the second input of which is connected to the output of the counter, the input of which is the first input of the control unit, the second input of which is the second input of the second element OR. FIG. 2