SU1559373A1 - Device for registering single signals - Google Patents

Abstract

The invention relates to a measurement technique, in particular, to recording pulse signals on a CRT screen, and can be used to indicate various signals, for example, when testing for single blows. The aim of the invention is to improve the accuracy of registration. The goal is achieved by the fact that the device contains a block of regulation 1 in amplitude and duration, consisting of two scaling amplifiers 2 and 4, a programmable frequency divider 8, as well as an analog-to-digital converter 9, a clock generator 12, an address counter 10, block 11 memory, CRT indicator 15, additionally two data buses, a real maximum generator 16, a counting trigger 20, a binary counter 21, a NOT element 19, an OR element 18 and a readiness trigger 22 are added. 1 il.

Description

The invention relates to measuring equipment, namely, to register pulse signals on a cathode ray tube (CRT) screen, and can be used to indicate various signals that can be converted into electrical form, for example, when conducting tests for single strokes.

The purpose of the invention is to increase the accuracy of registration.

The drawing shows a structural diagram of the proposed device.

This goal is achieved due to the fact that in a device containing a standardization unit for amplitude and duration, consisting of two scaling amplifiers and program recording in the memory unit information about the pulse signal itself, its history and aftereffects. Determining the maximum eliminates false positives, which increases the accuracy of registration, and recording all the information in one memory allows you to abandon the memory of the history of the pulse signal, which leads to a decrease in elemental costs.

The well-known recorder of shock acceleration parameters 15IEU-006 contains a special memory for the history of the pulse signal and determines the start of registration when the signal exceeds the level of 0.1 A, which leads to a decrease in accuracy and an expandable frequency divider, analog-to-digital converter (ADC), clock generator, counter addresses, a memory unit and an indicator on a CRT, two comparison buses are introduced, the register is de- actual maximum, register 0.5 A, where A is the maximum value of the amplitude that can be obtained from the ADC, a trigger for resolution resolution, a binary ¹ counter for N bits, where N is selected from the total memory capacity (memory capacity is 2 ^{N +} words) , the element is NOT, the element is OR, and the ready trigger.

The output of the element is NOT connected to the output of the OR element and the second input of the counter .N, the first input of which is connected to the output of the count resolution trigger, the third input is with the output of the programmable frequency divider, and the output is with the input of the ready trigger, the output of which is connected to the second input of the programmable divider frequency. The first input of the OR element is connected to the output of the first comparison circuit, the first input of which is connected to the output of the 0.5 A register, and the second input to the output of the actual maximum register and the second input of the second comparison circuit, the first input of which is connected to the ADC output and the first input of the real register maximum, and the output with the second input of the OR element and the third input of the register of the actual amplitude, the second input of which is connected to the output of the programmable frequency divider; 55 I ί

As a result of the introduction of blocks and new connections, the maximum of the pulse signal and the element costs are recorded.

2θ 'The device comprises a unit 1 for normalizing the input signal in amplitude and duration, consisting of a first scaling amplifier 2, a key 3, scaling capacitors 25 4, an attenuator 5, a second scaling amplifier 6, a feedback resistor 7, and a programmable frequency divider 8, ADC 9, address counter 10, memory block 11, generator 30 12 clock pulses (GTI), CRT indicator 13, register 14 0.5 A, first comparison block 15, register 16 of the actual maximum, second comparison block 17, element OR 18, element NOT 19, trigger 20 resolution with ETA, the counter 21 ready trigger 22, the order of the dial 23, the dial 24 the number, duration dial 25, the dial 26 0,5 amplitude information input 27, the inputs 28 Procedure scale, scale number

29, Duration of repeated counts

30, 0.5 amplitude 31.

At the same time, the unit 1 for normalizing the input signal in amplitude and duration contains the first scaling amplifier 2 in series with the key 3 and the block of scaling capacitors 4 in its feedback circuit 50, the attenuator 5, and the second scaling amplifier 6 with a resistor? in a feedback circuit, as well as a programmable frequency divider 8. The second scaling amplifier 6 of unit 1 is connected to the ADC 9, and the programmable divider 8 of the frequency of unit 1 is connected to the GTI 12, with the ready trigger 22, with the ADC 9, with the counter 21 and with the counter 10, the address is max input 17 compared to register input 16 of the actual maximum, the ADC output by the memory block 11 is connected by a CRT boat 13 to the second register 16 of the actual mA and to the input of the second neny block, the output of the register 14 0.5 A is connected to one of the inputs of the first comparison block 15, the second input of which is combined with second input of the second. the comparison unit and is connected to the output of the actual maximum register 16, and the outputs of the comparison units 15 and 17 are connected to the inputs of the OR element 18. In addition, the output of the second comparison unit 17 is also connected to the input of the actual maximum register 16, the output of the OR element 18 is connected to the inputs of the element HE 19 and the counter 21, the output of the element HE 19 is connected to the inputs of the counting trigger 20, the output of which is connected to the counter 21, the output of which is connected to the input of the ready trigger 22 and through the address counter 10 with the memory unit 11. The input 27 of block 1 is the information input of the device, the input 28 is connected to the order knob 23, which switches the key 3 of block 1, the input 29 is connected to the number knob, i.e. the input signal amplitude controller and controls the switching of the attenuator 5, the input 30 is connected to the input signal repetition timer and is connected to the input of the programmable divider 8 of the frequency of unit 1. Input 31 is the input of the counting task to the register 14 0.5 A and connected to the setter 26.

The device operates as follows.

In the absence of an information signal in the memory unit 11 at the address specified by the address counter 10, the zero code received from the ADC 9 is recorded.

The maximum value of the pulse signal is determined by the second comparison unit 17, which compares the current code obtained from the ADC 9 with the maximum code received earlier and recorded in the register 16 of the actual maximum. If the current value is greater than the previous one, the second comparison unit 17 generates a signal that allows writing the new value to register 1b of the actual

1559373 6 maximum. If the current value is less than the previous one, then the second comparison unit gives a signal to the element

OR 18. In parallel with the second comparison unit, the first comparison unit 15 compares the value recorded in the register 16 of the actual maximum with 0.5 A (half the amplitude of the input signal) recorded in the register 14 0.5 A, and gives a signal to the element OR 18, if the value of the actual maximum exceeds 0.5 A. As soon as both signals appear on the OR element, it generates a signal that passes through the HE 19 element and sets the count resolution trigger 20, the signal from the count resolution trigger 20 goes to counter N 21. Counter N21 counts 2 t acts that come from a programmable frequency divider 8 and generates a signal, which sets the trigger 22 ready. The latter prohibits the passage of clock pulses from a programmable frequency divider 8 and signals the end of the registration process.

The whole circuit is constructed in such a way that if the maximum is local, a reset signal arrives at counter N 21 and the circuit expects the actual maximum to arrive.

Writing to the memory unit 11 occurs cyclically, i.e. after the value is written to the last memory cell, the next value is written to the first cell. Since the capacity of the memory block 11 is 2 ^{1.1 + 1} or

2.2, it is not difficult to see that after writing the maximum code and starting the counter N, 2 more values will be written to memory block 11. Thus, exactly half the capacity of the memory unit 11 is occupied by the history and the beginning of the pulse signal to the maximum value, and the second half of the memory is occupied by the value of the pulse signal after the maximum value and aftereffect.

Information from the memory unit 11 is displayed on the CRT indicator 13, on which the recorded process is displayed.

Duration scaling is carried out by changing the quantization of the ADC 9, address counter 10 using a programmable counter-divider 8.

The controller 23 of the order controls the key 3, which replaces the capacitance in the feedback circuit ^{5 of the} scaling amplifier 2.

Normalization, the sensitivity of the sensor is carried out by the attenuator 5, which is controlled by the setter 24 numbers.

Claims (1)

Claim A device for recording single signals, containing a standardization unit for amplitude and duration, the first output of which is connected to the information input of an analog-to-digital converter, the address counter is connected in series, the memory unit and indicator, as well as the first trigger, the first unit are equal niya ,. OR or NOT elements, which means that, in order to increase the accuracy of registration, a second comparison unit, a second trigger, a counter, and two registers are introduced into it, and the second output of the normalization unit is connected to the analog-digital clock input the converter, with the inputs of the address and counter counter and with the write output of the second register, the input of the first trigger is connected to the output of the counter, the output of the OR element and the input of the element NOT are connected to the reset input, and the output of the second trigger whose input is connected to the output is connected to the enable input. uh NOT element, the inputs of the OR element are connected to the outputs of two comparison blocks and with the enable input of the second register, the first input of the first comparison block is connected to the output of the first register, and the second is combined with the input of the second comparison block and connected to the output of the second register, the second input of the second comparison block connected to the information input of the second register, with the output of the analog-to-digital Converter and with the input of the memory block.