SU1471098A1 - Device for determining dynamic characteristics of structures - Google Patents

Abstract

The invention relates to a testing technique and can be used in mechanical engineering. The purpose of the invention is to expand the functionality. Prior to testing, a test program and signal samples are entered into the programmable control unit, which during the test are fed to the object through an amplitude scaling unit controlled by a programmable control unit. The computing unit processes the response received from the object and calculates the dynamic characteristics. 3 il.

Description

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The invention relates to a testing technique and can be used in mechanical engineering.

The purpose of the invention is to expand the functionality of the device by generating excitation signals of a given arbitrary shape.

Figure 1 shows the block diagram of the device; Fig. 2 is a diagram of a programmable control unit; FIG. 3 is a diagram of a digital code transmission control block.

The device contains a programmable control unit 1, an excitation signal generation unit 2 consisting of a serially connected digital control unit 4. A digital code transmission, the second input of which is connected to the output of timer 3, a digital-to-analogue converter (DAC) 5 and an amplitude scaling unit 6, exciter 7 exciter, 8 installed object with placed

sensors 9 are connected to the signal inputs of the analog-digital converter (ADC) 10, the control input of which is connected to the programmable control unit 1, and the output - to the input of the operational memory unit 11 serially connected to the calculation unit 12, controlled which input is connected to the programmable control unit 1. The control inputs of the timer 3, the amplitude scaling unit 6, the A / D converter 10, the operating memory unit 11 and the first input of the digital code transmission control unit 4 are connected to the outputs of the programmable control unit 1.

The control unit 1 (phi; -. 2) consists of the census scheme for the next recording of the test program for service registers, the operational memory unit 13, delay element 14, the 15-cycle counter and the 16 clock generator (L

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pulses, the census scheme includes a trigger, 17 controls, the output of which is connected to the control inputs of the nporpaMNbi record length counter 18, the test and the counter 19 of the current address of the test program entry. The output of the counter 19 of the current write address of the test program is connected to the first address input of the RAM block 13, the output of the write length counter 18 is connected to the input of the address decoder 20, and the transfer output is fed to the timer enable input

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recording the test program and the current address of the test program.

The counting input of the counter 15 is connected to the output of block 4, the overflow output of the counter of 15 cycles is connected to the third S-input of the control trigger 17, the control input of the main memory block 11 and the prohibition input of the ti-Q measure 3.

The digital code transmission control unit 4 (FIG. 3) consists of a sample length counter 25, the counting input of which is connected to the counting input

3 and on the trigger 17 control, 15 counter 26 of the current address of the sample

as well as through the element OR 25 is fed to the input of the download of the same counter,

The first output of the address decoder 20 is connected to the first inputs of the characteristics analysis circuits 20 22 and 23 End of the test program and prohibition of processing performed on the AND elements, the second output is connected to the load input of the counter 15 of the cycle, and the third to the sixth outputs - to the control the inputs of blocks 3,4,6. The output element And 23 is connected to the control input of the computing unit 12, and the code of the element And 22 is connected to the second S input of the control trigger 30 17. The signal through the OR 24 element is fed to the download input of the counter 19 of the current address of the record and through the OR 21 element to the download input of the counter 18 of the recording length. ,five

A start signal is applied to the second input of the OR element 24 and the first control trigger 17 connected to it by the first S-input.

and with the output of timer 3 through the delay element 27, the overflow output — with the counter input of 15 cycles, and also through the first input of the OR element 28 — with the load input of the same counter and the load input of the count 26 of the current sample address. The second input element OR 28 is connected to the output of the record length counter 18. The third input element OR 28 through the element 29 of the delay signal is received. The control input of the register 30 of the initial sample address is connected to the third output of the decoder 20, and the information input of this register is connected to the output of the RAM block 13. The output of register 30 is connected to the information input of the counter 26 of the current address of the sample, and the output of the latter is connected with the second address input of the RAM block 13.

The output of timer 3 is connected via a delay element 27 with a control input to the register 31 of the signal sample.

The second address input of block 13 one-up Information input of this register

The memory is connected to the information output of block 4. The output of timer 3 is connected to the control input of the ATP 10 and, through delay element 14, to the control input of block 13 of the operational memory.

The output of the RAM block 13 is connected to the information input of the cycle counter J5, the second inputs of the feature analysis circuits 22 and 23, End of the program and the Prohibition of processing and the information inputs of the digital code transmission control block 4; yes,

The output of the generator 16 clock pulses is connected to the clock input of timer 3 and the counting inputs of counters 18 and 19, respectively

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connected to the output of the RAM block 13, and its output to the first input of the adder 32, the second input of this adder is connected to the output of the register 33 of the constant component of the signal, and its output to the input of the CAP. The information input of the DC register 33 is connected to the output of the RAM block 13, and the control input of this register is connected to the sixth output of the decoder 20.

The device works as follows.

Prior to testing, the RAM block 13 sends signal samples (one period for each type of periodic signal) that will be used in the tribute with timer 3 output through delay element 27, overflow output - with counter input 15 cycles, and also the first input of the OR 28 element is with the download input of the same counter and the download input of the count 26 of the current sample address. The second input element OR 28 is connected to the output of the record length counter 18. The third input element OR 28 through the element 29 of the delay signal is received. The control input of the register 30 of the initial sample address is connected to the third output of the decoder 20, and the information input of this register is connected to the output of the RAM block 13. The output of register 30 is connected to the information input of the counter 26 of the current address of the sample, and the output of the latter is connected with the second address input of the RAM block 13.

The output of timer 3 is connected via a delay element 27 with a control input to the register 31 of the signal sample.

Information entry of this register

connected to the output of the RAM block 13, and its output to the first input of the adder 32, the second input of this adder is connected to the output of the register 33 of the constant component of the signal, and its output to the input of the CAP. The information input of the DC register 33 is connected to the output of the RAM block 13, and the control input of this register is connected to the sixth output of the decoder 20.

The device works as follows.

Prior to testing, the RAM block 13 records samples of signals (one period for each type of periodic signal) that will be used in this

a test for generating the excitation signals, and a test program. Each program entry describes a specific excitation signal and contains information about the type of the periodic component of the signal (with reference to the corresponding sample) and its parameters (frequency, amplitude, constant signal level, duration) signal, expressed as the number of cycles of this sample). The lengths of the samples and test program records are fixed and do not depend on the type of signal. The first word of the record may contain the signs End of program and Disallow processing. The signals used to calibrate the exciter of oscillations, transfer the object to another static position, and visual analysis of the development of this excitation signal are not processed. On the basis of the end of the program, the amma test program begins to be reworked from the first record. This process is repeated until a Stop signal is received from the test operator’s console (not shown).

Upon receipt of the Start-up signal from the test operator’s console, the census block of control unit 1 begins to work, which rewrites the information from the test program record to the registers of the corresponding blocks. The counter 15 records the number of sample processing cycles, the register 30 is the initial address of the sample for timer 3, the setting corresponding to the time interval between two consecutive digital signal values, the scaling unit 6 for the magnitude of the excitation signal, and for register 33 the constant value component of the excitation signal.

The census scheme works as follows. The Start signal goes to the first S input of control trigger 17. Trigger 17 enables the counters 19 of the current write address and 18 record length to operate. Counting pulses on the counters 18 and 19 are received from the generator 16 clock pulses. The signal from the counter 18 is fed to the decoder 20 and allows the census of the next word of the test program entry in the appropriate register. The address of this word is in the block-13 operative memory.

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These are indicated by the current state of the counter 19 of the current address of the entry. After the census of all words of the next test program record from the transfer output of counter 18, a pulse arrives at the R input of trigger 17, which prohibits the operation of counters 18 and 19, and the initial state of counter 18 resumes at the same time. Reading the next test program record will be possible only after exhaustion no counter 15 cycles, the output name-, the pulse of which is fed to the third S-input of trigger J 7 and allows the counters 18 and 19 to work. If the first word of the next record contains the sign End, of the program, from the output of the analysis circuit 22 The signal arrives at the second S-input of the trigger 17 and through the OR element 24 to the load input of the counter 19. As a result of the load, the current state of the counter 19 is replaced with the start address of the test program, and the first record of the test program begins to be copied again.

At the end of the census of the first record of the test program by the census scheme, the Lusk signal through the time determined by delay element 29 and sufficient for the census block 1 to work triggers to the load inputs of counters 25 sample length, 26 current sample address and control g the input of timer 3, as a result of which a constant value of the sample length is entered into the counter 25, the value 26 of the initial address of the array of sample values from the register 30 is entered into the counter 26, which is entered there by the block I census scheme, and the timer is started 3. Subsequent recording of information in counters 25 and 26 occurs on a signal received from the transfer output of counter 18 for the record length. Upon arrival of the counting pulse from timer 3, the contents of the sample length counter 25 are reduced by one, and the contents of the counter 26 0 of the current sample address are incremented by one and indicate the address of the next sample value in the RAM 13. On a signal from timer 3, after a time determined by g delay element 27 and sufficient to execute the read cycle of memory block 13, the current sample value is rewritten into register 31 and from it goes to first in x.

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adder 32. The other input of this adder receives the value of the constant component of the excitation signal in register 33. The resulting value comes from the output of adder 32 to the input of the DAC 5.

When the sample length counter 25 is exhausted from the transfer output of this counter, a signal is fed to the load inputs of counters 25 and 26 and the counter input of counter 5 is overwritten by the contents of counters 25 and 26, the contents of counter 15 are reduced by one and the next excitation period begins working. The response of object 8 to this excitation signal from sensors 9 is converted by ADC 10 by a signal from timer 3 and is recorded in block 1 of the operational memory. When the 15-cycle counter is exhausted, timer 3 stops, as a result of which the object stops excitation signal and reception of a response from the object, after which the census scheme of control unit 1 reconfigures the corresponding units of the device to the transmission of the next excitation signal in accordance with the test program. In parallel with the transmission of the excitation signal, the computing unit 12 processes (if there is no prohibition on processing from the analysis circuit 23 if there is a sign Disabling processing), the response received from the object to the previous excitation signal and calculates the dynamic (amplitude and phase) frequency characteristics.

Claims (1)

Invention Formula A device for determining the dynamic characteristics of objects, containing an excitation signal generation unit, an excitation exciter, sensors installed on the product, and a series-connected multichannel analog-to-digital converter (AC1), the measurement inputs of which are connected to the sensors, a memory block and a block computations, characterized in that, in order to expand the functional capabilities of the device by generating arbitrary-type excitation signals, it is equipped with a programmable eye control, consisting of another circuit census eight 0 0 five 0 five 0 five 0 five recording the test program for service registers, the first delay element, the second RAM block, the loop counter and the clock pulse generator; the excitation signal generation unit contains a timer connected in series to the digital code transmission control unit, digital-to-analog converter (D / A converter) and amplitude scaling unit; the census scheme includes a control trigger, the output of which is connected to the control inputs of the current record address and record length counters, the output of the current record address connected to the first address input of the second memory unit, the output of the write length counter is connected to the address of the address decoder, and the transfer output is connected to the timer enable input, the control trigger R input and the first input of the first OR element, the first output of the address decoder is connected to the first inputs feature analysis blocks End of test program and Disabling processing, second output - with load input of loop counter, output of characteristic analysis block End of test program is connected to second S-BXO control house and via From the first input of the second element OR - with the download input of the counter of the current write address and the second input of the first element OR whose output is connected to the download input of the record length counter, the output of the clock pulse generator is connected to the clock input of the timer and the counting inputs of the current address counters record and record length, the overflow output of the loop counter is connected to the third S input of the control trigger, the control input of the RAM block and the timer inhibit input, the control unit for transmitting the digital code, consists of the current address and sample length ratios, the second and third delay elements, the third OR element, the sample initial address registers, the periodic and constant signal components and the adder, the load addresses of the address counters and the sample length through the first input of the third OR element. To the overflow output of the counter the sample length and the counting input of the cycle counter, the second input of the third element OR is connected to the transfer output of the recording length counter, the third input of the third ISH1 element is connected through the second delay element to the second input of the second OR element and the first S-input of the control trigger, the control input of the sample initial address register is connected to the third output of the address decoder, and the output of this register is connected to the information input of the current sample address counter, the output of which is connected to the second address input of the second operational block the memory, the first and second inputs of the adder are connected to the outputs of the registers of the periodic and constant components, its output - to the input of the LLL, information inputs of the cycle counter, registers of the initial address a, periodic and constant component and a second 7109810 The inputs of the attributes analysis blocks. The end of the test program and the Inhibition of processing are connected to the output of the second RAM block; the fourth, fifth, sixth outputs of the address decoder are connected to the control inputs of the amplitude scaler, respectively, 10 of the register of a constant component; the control input of the A / D converter; the control input of the second RAM block — through the first delay element; counting inputs — are connected to the timer output; 15 counters of the address and the sample size and the control input of the register of the periodic component are through the third delay element, the output of the characteristic analysis block. The prohibition of processing is connected to the control input of the calculation block. 1 zi nineteen 13 ts sixteen