SU1500827A2 - Sensing device having automatic calibration function - Google Patents

Abstract

The invention relates to a radio measuring technique and can be used for automatic calibration in digital devices, such as recorders and oscilloscopes. The invention improves calibration accuracy by reducing the effect of noise. The calibration signal is repeatedly converted to ADC 3, the resulting codes are summed by adder 12 with the codes from the sum register, and then divided by the number of summations in divider 14. The resulting average code is written into calibration memory 10. Due to the static accumulation of measurement results, the calibration accuracy is improved without taking into account the effect of noise, and the effect of ADC noise on the calibration accuracy is eliminated.

Description

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31500827

1nobreteine. relates to radio measuring equipment, can be used for automatic calibration in digital devices, such as recorders and oscilloscopes, and is an improvement of the device according to the author. St. No. 1384953.

The purpose of the invention is to improve the calibration accuracy by reducing 10 the influence of noise.

Figure 1 shows a block diagram of a recording device with automatic calibration; figure 2 - timing charts of his work. 15

Automatic calibration registration device contains input switch 1, amplifier 2, analog-to-digital converter (ADC) 3 |

connected to the inputs of the comparator 7 codes and multiplexer 8,

The device works as follows.

In the Calibration mode, the input of the amplifier 2 is connected to the input of the ACI 5 through the input switch 1 and the calibration voltage is applied to the input of the amplifier 2 and then to the ADC 3. In real systems, noise is superimposed on the calibration signal (see Fig. 2a). A single measurement of the calibration voltage, for example, at point t, has a large error due to noise. You can eliminate this drawback by repeatedly measuring the calibration signal and then averaging the measurement result. At the same time, using a teo-storage device (memory) 4, digital filtering digital noise power, analogue analogue converter (DAC) 5, 6 frequency switch, 7 code comparator, multiplexer 8, calibration mode trigger 9, calibration memory 10 11, adder 12, amount register 13, divisor 14 code, amount counter 15. Moreover, the input - switch 1, amplifier 2 and ADC 3 are connected in series

decreases with respect to the power of the desired signal in mW times, where N is the number of measurements.

In the proposed device, the averaging of calibration coefficients is implemented as follows.

The code at the input of the DAC 5 is changed with the frequency fu, cin / W where N. is the recalculation coefficient of the counter 15, and

admittedly, the outputs of the ADC. 3 are connected to the input, - 30 gate ADC input 3 enters

connected to the inputs of the comparator 7 codes and multiplexer 8,

The device works as follows.

In the Calibration mode, the input of the amplifier 2 is connected via the input switch 1 to the output of the ACI 5 and the calibration voltage is applied to the input of the amplifier 2 and then to the ADC 3. In real systems, noise is superimposed on the calibration signal (see Fig. 2a). A single measurement of the calibration voltage For example, at point t it has a large error due to noise. You can eliminate this drawback by repeatedly measuring the calibration signal and then averaging the measurement result. In this case, according to the theory of digital filtering noise power

decreases with respect to the power of the desired signal in mW times, where N is the number of measurements.

In the proposed device, the averaging of calibration coefficients is implemented as follows.

The code at the input of the DAC 5 is changed with the frequency fu, cin / W where N. is the recalculation coefficient of the counter 15, and

The RAM 4 and, through the series-connected adder 12, the register 13 and the divisor 14 codes are with the inputs of the comparator 7 codes and multiplexer 8, the second input of which is connected to the 35 output of the memory 4, and the control input is connected to the trigger output 9 of the mode. calibration, the inputs of the calibration memory 10, the switch 11 and the input switch 1, the third input of which is connected to. 40 by the output of the DAC 5, the second output of which is connected to the data inputs of the calibration memory 10, the second input of the D / A converter 5 is connected to the trigger inputs 9 of the calibration mode frequency fu, c (ri b result for time from O to tj-, Fig 26) at the output ADC 3 generates N codes for the same calibration voltage. These codes are sent to the first input of the adder 12. To the second input of the adder 12. the sum code from the register 13 of the sum arrives. These two codes are added to the adder 12 and recorded with the frequency to the sum register 13. The last one, by each pulse, fu, an / N is reset to zero. In sum, in register 13 of the sum after every N pulses of the hour, memory 4 and switch 6 frequencies, you (45 tons the sum of the U-instantaneous values of the transformed ka is formed, - the lib voltage of one level. Dividing the sum by N in the divider 14 codes, we obtain the average code for this calibration voltage, which is then recorded in the calibration memory 10, the process of calibration calibration memory 10 is continued until the output of the divider

the stroke of which is connected to the clock input of the charger 4, another input of the trigger 9 of the calibration mode is connected to the output of the code comparator 7, the output of the multiplexer 8 is connected to the input of the calibration charger 10, the other input of which is connected to the output of the switch 11, the first input of which is connected to the peeter

values of the transformed ka, - librovochnogo voltage of one level. Dividing the resulting amount by N in the code divider 14, we obtain the average code for this calibration voltage, which is then recorded in the calibration memory 10. The process of calibration calibration memory 10 continues until the output divider

the input of the DAC 5, the reset input to the 13 cyMMJii register and the output of the 15 sum counter, ° D according to the code, the corresponding input of which is connected to the input line - the upper boundary of its range. When the frost clock frequency of the DAC 3, clock input. AIUI 3 n register 13 sums, and others-L1-gtel 14 code

On the appearance of this code, a comparator 7 codes is triggered, resetting (the calibration mode trigger 9, that the frequency fu, c (ri b result for time from O to tj-, (FIG. 26) the output of ADC 3 is formed by N codes for one and same calibration voltage values. These codes are sent to the first input of the adder 12. The second input of the adder 12. receives the sum code from the sum register 13. These two codes are added in the adder 12 and are recorded with a frequency in the sum register 13. The last one by each pulse fu, an / N is reset to zero. Thus, in register 13, the sums of each N pulses h

values of the transformed ka, - librovochnogo voltage of one level. Dividing the resulting amount by N in the code divider 14, we obtain the average code for this calibration voltage, which is then recorded in the calibration memory 10. The process of calibration calibration memory 10 continues until the output divider

° D on Wits code corresponding to the upper limit of its range. With

° D on Wits code corresponding to the upper limit of its range. With

on the appearance of this code, a comparator of 7 codes is triggered, resetting (trigger 9 of calibration mode, which is re I I I And I I I I I I I I I I I I I I I I I M I I I I I I I

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FIG. Z

Claims (1)

Claim Registration device with automatic calibration according to ed. St. we are connected to the clock input of an analog-to-digital converter, the input of the sum counter and the clock line. Fie. 2