SU1675904A1 - Statistical analyzer - Google Patents

Abstract

The invention relates to computing and can be used in a), signal processing devices, analyzers, while providing a calculation of scattergrams of input processes, as well as the sorting of input data on a given scale. The purpose of the invention is to increase the speed by reducing the number of analyzed input numbers. To solve this problem, the analyzer contains a clock pulse generator, a counter, three 2I-OR elements, an ADC, a comparison unit, an adder, a multiplication unit, two NOT elements, a pulse driver, a delay element, a block of elements AND, a block of elements EXCLUSIVE OR, a block of subtracting and memory block. 1 il.

Description

The invention relates to computing and can be used in signal processing devices, measuring devices and sorting devices.

The purpose of the invention is to increase speed.

The drawing shows the functional diagram of the device.

The analyzer contains an A / D converter A / D converter 1, subtraction unit 2, block 3 elements EXCLUSIVE OR, comparison unit 4, multiplication unit 5, counter 6, clock generator 7, memory block 8, information output of the analyzer 9, adder 10, block 11 AND elements, first element 2И-OR 12, first 13 and second 14 elements NOT, element OR 15, shaper 16 pulses, second 17 and third 18 elements 2И-OR, element 19

delays, information input 20 of the device, input 21 of setting the initial value of the mathematical expectation of the analyzer, input 22 specifying the width of the differential range of the analyzer, clock input 23 of the device, input 24 of the initial installation of the mathematical expectation of the analyzer, input 25 resetting the analyzer, input 26 starting the analyzer, output of block 8 the memory is connected to the first input of the adder 10, the output of the counter 6 is connected to the address input of the memory block 8, the information input 20 of the analyzer is the input of the A / D converter 1, the output of which is connected to the input y enshaemogo subtracting unit 2, the subtrahend input which is connected to the input 21 setting an initial value of the expectation of the analyzer, the information output of the subtractor unit is coupled with a first group of inputs

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block 3 elements EXCLUSIVE OR, the transfer output of the subtraction unit is connected to the second group of inputs of block 3 elements EXCLUSIVE OR, the output of which is connected to the first input of comparator 4, the second input of which is connected to the output of multiplication unit 5, the multiplicative input of which is connected to input 22 of the width setting the differential range of the analyzer, the multiplier input of the multiplier 5 is connected to the output of counter 6, the summing input of counter 6 is connected to the output of the generator 7 of counting pulses and to the first input of the first group of inputs of the first el 2I-OR 12, the second input of the first group of inputs of which is connected to the input of the first element NOT 14, the first input of the element OR 15 and the input 25 of the analyzer reset, the second input of the element OR 15 is the analyzer start input 26, the output of the first element 14 is connected with the control input of block 11 of elements AND, whose information inputs are connected to the output of adder 10, output More of block 4 of comparison is connected to the start input of the counting pulse generator, with the first input of the second group of inputs of the first element 2 AND-OR 12, the second input of the second group the inputs of which is the clock input 23 of the analyzer and is connected to the synchronization input of the A / D converter 1 and the first input of the first group of inputs of the second element 2 AND-OR 17, the second input of the first group of inputs of which is connected to the third input of the second group of inputs of the first element 2 AND-OR 12, with the clock input of the multiplication unit 5, with the input 24 of the initial installation of the analyzer expectation and with the first input of the first group of inputs of the third element 2 AND-OR 18, the second input of the first group of inputs of which is connected to the transfer output of the subtraction unit 2, the output pulse generator 16 is connected to the first and second inputs of the second group of inputs of the second element 2 AND-OR 17, the output of which through the delay element 19 is connected to the reset input of the counter 6, the transfer output of which is connected to the first input of the second group of inputs of the third element 2 AND-OR 18 The second input of the second group of inputs of which is connected to the input of the pulse former 16 and with the output of the OR 15 element, the output of the third element 2 AND-OR 18 is connected to the high-order bit of the address input of the memory block 8, the output of the first element 2I-OR 12 is connected to the input at NO 13, the output of which is connected to the read / sign input of memory block 8.

The analyzer works as follows.

There are three modes of operation: erase, analyze and read. In the erase mode

input 25 receives a signal log. 1, which is fed to the second input of the second group of inputs of the first element 2 AND-OR 12 and allows the output of the element 2 AND-OR 12 to pass the clock pulses from generator 7 to the first input of the first group of inputs of the element 2 AND-OR 12. From the output element 2 AND-OR 12 through the first element NOT 13 pulses arrive at the read / write input of memory block 8 and allow

record At the same time, the pulses from generator 7 arrive at the clock input of counter 6, whose output bits of N are directly connected to the N address bits of memory block 8, and the N-H output is connected

to the third input of the third element 2 AND- OR 18. Since the second input of the second group of inputs of the element 2 AND-OR 18 is connected to the output of the element OR 15, there is a Log on it in erase mode. 1, which means N + 1,

on the output bit of the counter 6 is connected through the element 2 AND-OR 18 to (the N + IJ address bit of the memory block 8. At the moment the erase mode is activated, the pulse shaper 16 is started through the OR 15 element, from which the pulse through the second element 2 AND-OR 17 sets the counter 6 to the zero state. Potential Log. 1 from input 25, the passage through the second element is NOT 14. converted

in the log. O, which blocks elements 11, in connection with which. The information inputs of memory block 8 are received zeros. These zeros are written in turn into all memory locations whose addresses are sequentially assigned by the counter 6.

In the analysis mode, input 24 receives the Log signal, 1. Synchronously with the clock pulses, input 23 converts the analog signal to a digital one.

the code § in the ADC 1. The code Јi is fed to the input A of block 2 of the subtraction, to the input of which the code of mathematical expectation M arrives. In block 2 of the subtraction the difference | i M is determined. If Ј, is M 0, then the output

transfer of block 2 subtraction is formed Log. O, which is fed to the second inputs of block 3 of the EXCLUSIVE OR element, which in this case passes the code from the output of block 2 subtraction without changes. If § is M 0, then a log is formed at the output of the transfer of block 2 subtraction. 1, which translates the elements EXCLUSIVE OR 3 into the inversion mode, therefore, at the output of block 3, the difference modulus is formed

| Јi - Ml 0, which is fed to the input B of block 4 of the comparison. The first clock pulse from input 23 passes through the second element 2 AND-OR 17, since the last one is open. 1 from input 24, and resets counter 6 to zero. The zero code of the counter 6 is fed to the input of the block 5, therefore, at its output there is a zero code which is fed to the input A of the block 4 of the comparison. Since in most cases | § - М I 0, then at the output A B of the comparison block 4 there is a Log. O, the generator 7 is not blocked, its impulse transfers the counter 6 to the log. 1. In block 5, the value of the differential analysis range code AM, input to analyzer input 22, is multiplied by 1, the multiplication result in the comparison block is compared with the value | Јi -Ml or fЈi -Mi DM, then at output AV of block 4 logs 1, generator 7 is blocked, this Log. 1 is fed to the third input of the first element 2 AND-OR 12 and together with the log. 1 from input 24 permits the passage of a clock pulse from input 23 to the output of element 2 AND-OR 12 and then through the element NOT 13 to the read / write input of memory block 8.

Information from the output of the memory block 8 is fed to the input of the adder 10, in which this code is summed with the log. 1, and the increased number is written to memory block 8 at address 1. If | Ј, -Ml L M, then the counter 6 at the next clock pulse of the generator 7 goes to state 2, the output of block 5 is 2 DM, and then 3 AM-KA M until it becomes | Јi - M | To AM. Then, according to the above scheme, the number written at address K in block 8 of memory will be recorded. The AN + I address of the memory block is a sign, its concept means (conditionally) that there is not only a cell with the number K (by address resolution), but the numbered cell with the number-K. The sign is determined by the state of transfer in block 2. Signal The transfer enters the first input of the first group of inputs of the third element 2 AND-OR 18 and through it to the address input of the memory block 8, therefore, the sign is taken into account when writing to the memory block.

If the input sample size is 14.1 "2N, the input samples are distributed in 1 cells of memory block 8, and the probability of two numbers falling into one cell is very small and when reading from the memory, the input numbers are arranged in ascending order those. the analyzer provides a ranking of input values.

In the case of the sample size I 2N + 1, the analyzer provides a calculation of the histogram of the input numbers, you can shift the center of the histogram M and its step AM

In the erase mode, the Log signal is sent to the analyzer input 26. 1. At the same time, the pulse shaper 16 is started through the OR 15 element, the pulse of which through the AND-OR element 2 and the delay element 19 sets the counter to zero 6. Since the multiplication unit is blocked in the absence of the analysis mode, there is an information zero at its output the output of comparator 4 is also zero and

Claims (1)

5 generator 7 clock pulses unlocked. Counter 6 sequentially polls the addresses of memory block 8, and (N-H) -u the bit of counter 6 in read mode via element 2 is AND-OR 18 connected to (N + 1) 0 th address input of memory block 8. A statistical analyzer comprising a memory unit, an adder, a counter, a comparison unit, an OR element, a delay element, a clock generator, the output of the memory unit is connected to the first input of the adder, the second input of which is the input of the analyzer logic unit, the output The counter is connected to the memory input of the memory unit, characterized in that, in order to improve speed, a subtraction unit, an EXCLUSIVE OR element block, a multiplication block, an AND block 5 three elements 2I-OR, a pulse shaper, two elements NOT and an analog-to-digital converter, the information input of the analyzer being the information input of an analog-digital 0 converter, the output of which is connected to the input of the decremented subtraction unit, the input of the subtracted which is connected to the installation input of the initial value of the mathematical expectation of the analyzer, 5, the information output of the subtraction unit is connected to the first group of inputs of the block of EXCLUSIVE OR elements, the transfer output of the subtraction unit is connected to the second group of inputs of the block of EXCELS ORT elements, whose outputs are connected to the first input of the comparison unit, the second input of which is connected to the output of the multiplication blocks, multiplicative input which is connected to the input of setting the width of the differential range of the analyzer, the input of the multiplier of the multiplying unit is connected to the output of the counter, the summing input of the counter is connected to the output of the generator and with the first input of the first group of inputs of the first element 2I-OR, the second input of the first group of inputs of which is connected to the input of the first element NOT, the first input of the OR element and the reset input of the analyzer, the second input of the OR element is the start input of the analyzer, the output of the first the element is NOT connected to the control input of the AND block, the information inputs of which are connected to the output of the adder, the output of the More comparison block is connected to the trigger input of the clock, with the first input of the second group the input in the first element 2I-OR, the second input of the second group of inputs of which is the clock input of the analyzer and connected to the synchronization input of the analog-digital converter and the first input of the first group of inputs of the second element 2I-OR, the second input of the first group of inputs of which is connected to the third input the second group of inputs of the first element 2И-OR, with the clock input of the multiplier unit, with the input of the initial installation of the analyzer's expectation and with the first input of the first group of inputs of the third element 2И-OR, the second input of the first group which consists of nN connected to the transfer output of the subtraction unit, the output of the pulse generator is connected to the first and second inputs of the second input group of the second element 2I-OR, the output of which is connected via the delay element to the reset input of the counter, the transfer output of which is connected to the first input of the second input group of the third element 2I- OR, the second input of the second group of inputs of which is connected to the input of the pulse former and with the output of the OR element, the output of the third element 2И-OR is connected to the high-order bit of the address input of the memory unit, the output of the first electric The terminal 2I-OR is connected to the input of the second element NOT, the output of which is connected to the input of the read-write memory block. hch 25 ib