SU1319028A1 - Digital pulse repetition frequency multiplier - Google Patents

Abstract

The invention relates to computing and can be used in the construction of low-frequency signal processing devices. The purpose of the invention is to increase the multiplication accuracy by increasing the order of extrapolation of the period of the multiplied frequency. The multiplier contains reversible counters 1, 2, 3, 4, 6, a register 5, a clock generator 7, a frequency divider 8, information input 9, a group of delay elements 10 and an output 11 with corresponding links. In the multiplier, based on the measurement of several periods (depending on the extrapolation order), the value of the expected period is determined and the expected frequency is multiplied, 1 sludge. I (L 00 00

Description

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The invention relates to computing technology and can be used in the construction of low-frequency signal processing devices.

The purpose of the invention is to increase the multiplication accuracy by increasing the type of extrapolation of the period of the multiplied frequency.

The drawing shows a functional diagram of an example of a digital pulse frequency multiplier having an extrapolation order.

The frequency multiplier contains the first 1, second 2, third 3 and fourth 4 reversible counters, register 5, fifth counter 6, clock generator 7, frequency divider 8, information input 9, group of elements 10 of deceleration and output 11, with generator output 7 clock pulses are connected to the subtraction input of the reversible counter bis by the input of the frequency divider 8, the first output of which is connected to the addition input of the reversible counter 4, the second output of the frequency divider 8 is connected to the input of the subtraction of the reverse counter 3, the third output of the divider 8 you are connected to the input adder down counter 2, the fourth output of the frequency divider 8 is connected to an input of subtractor -reversivnogo counter 1, in which the set input N.OL connected to the output of the fourth delay element 10 groups. The write enable inputs of the second 2, third 3, and fourth 4 reversible counters are connected respectively to the outputs of the third, second, and first delay elements 10 of the group. The overflow output of the reversible counter 6 is connected to its recording resolution input and to the output 11 of the frequency multiplier, information input 9 of which is connected to the inputs of the group 10 delay elements and the recording resolution of the register 5, the discharge outputs of the reversible counter 1 are connected respectively to the reversible counter installation inputs 2, the discharge outputs of which are connected respectively to the installation inputs of the reversible counter 3, the discharge outputs of which are connected respectively to the installation inputs of the reverse vnogo counter 4 The discharge outlets are connected respectively to the inputs of register bits dnymi 5 The discharge outlets which

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connected respectively to the installation inputs of the reversible counter 6. A pulse frequency digital multiplier operates as follows

in the way

At the input 9 of the multiplier receives a sequence of pulses of a multiplied frequency F.

With the arrival at input 9 of each of these pulses, the information from counter 4 to register 5 is first copied, then with a slight delay (for the time of writing information from counter 4 to register 5) - from counter 3 to counter 4, then from counter 2 to counter 3 and from counter 1 to counter 2.

After resetting the counter 1 post

0

Feeding on his subtractive input impulse „f. sy with frequency where g is frequency

m

pulses of the generator 7 clock pulses (F. About m - the ratio of the frequency divider 8, change its content. To arrive at the input 9 of the next pulse, the code in the counter 1 corresponds to the time between the first and second input pulses, i.e. - do T „,, and is transferred to counter 2. The summing input of counter 2 is received from the additional output of the divider

5 pulses with a frequency of 4, where 4 m

with a fourth-degree binomial coefficient. In this case, by the time of arrival of the third input pulse at the output of counter 2, a number proportional to 4 T "is formed. }, which is transferred to counter 3. (T. is the time between the second and third input pulses).

On the subtracting input of this counter divider 8 frequencies are received

 impulses with a frequency of 6, where 6, m

The fourth fourth-degree binomial coefficient, therefore, by the arrival of the fourth input pulse, the number corresponding to 6 T "., + 4T" ..- T., (T "., is the time between the third and fourth input pulses) is generated. The number is transferred to the information input of the counter 4, on

from the summing input of which comes from the divider 8 pulses of frequency

4, forming at the output of the counter

m

ka 4 by the time of arrival of that input pulse number 4Т „-6Т„., + 4Т .Т „., where T p is the time between the fourth and fifth input pulses. This number is the expected value of the period T ,, obtained by extrapolation of the third order taking into account the values of the four periods preceding it.

The number 1 is stored in the register.

5, and with each reset of the subtraction counter 6, is entered into the counter as an initial value. Pulses from the counter output

6 are multiplier output pulses. The counting input of the counter 6 pulses from the generator 1 clock pulses with a frequency f, therefore, the follow-up period of the output pulses of the proposed multiplier is equal to

T-jjii. and their frequency is mF. The maximum delay of the delay element must be less than the period of the pulse following, arriving at the counting input jr "ha of counter 2, i.e. less than -v-,

so that the state of counter 2 in the process of transferring codes changed by no more than one. There is a kind of pipeline processing of information, as a result of which, at the moment of arrival of the next input pulse at the output of register 5, it is prepared for installation in counter 6, a code that takes into account the values of the four preceding periods, and at the inputs of counters 2–4, codes are set , which are intermediate results of the calculation of the extrapolated period. A change in the counting direction of all the 40 chick counts to the opposite does not affect the operation of the device.

Similarly, extrapolation of some other order is realized.

At the same time, the higher the extra-45 polishing order, the more precisely the frequency of the input pulses is multiplied.

Claims (1)

Invention Formula Digital pulse frequency multiplier, comprising a clock pulse generator, first and second reversible counters, register VNIIPI Order 2513/43 Circulation 672 Subscription Proizv.-poly. pr-tie, g, Uzhgorod, st. Project, 4 five 0 five 0 r 0 5 0 5 0 and a frequency divider, the information input of the multiplier is connected to the register write enable input, the bit outputs of which are connected respectively to the setup inputs of the second reversible counter, the overflow output of the second reversing counter is connected to its same write enable input and the multiplier output, the clock pulse output is connected with the subtracting input of the second reversible counter and with the information input of a frequency divider, characterized in that, in order to increase the multiplication accuracy by raising the order of extrapolation of a period of multiplied frequency, a group of p + 1 delay elements and p additional reversible counters (where p is an extrapolation order) are entered into it, the counting inputs of which are from the first to the pth, respectively, connected to the outputs of the frequency divider, the signals on which are proportional from the p-th to the first binomial coefficients, and the output of the frequency divider, the signals on which are proportional to the (p + 1) th binomial coefficient, are connected to the counting input of the first counter, with the counting input of each () -ro counter (wherekO, 1, ..., p-1) will be the input of the input at k О and even and the input of the subtraction at k odd, the bit outputs of the first reversible counter are connected respectively to the installation inputs of the first additional counter, the bit outputs of the hygro i-ro additional the counter is connected respectively to the installation inputs (i + 1) -ro of the additional counter (where i 1 ,, .., р-1), the discharge outputs of the p-th additional counter are connected respectively to the discharge inputs of the register, the inputs of the delay elements of the group are connected with information input multiplied Alt, the outputs of the delay elements from the first to the nd group are connected respectively to the recording resolution inputs of additional counters from the pth to the first, the output of the (p + 1) -th delay element of the group is connected to the installation input in O of the first reversible counter.