SU1254479A1 - Pulse number multiplier - Google Patents

Abstract

The invention relates to computing and can be used in constructing arithmetic devices of digital computers, in blocks of control and information processing. The aim of the invention is to increase the speed in the case of multiplying the number of pulses by 9. In the multiplier, which contains a delay element connected to the input and summing counters connected in series, the BAN element, the decoder zero and the readout counter, the input of which is connected to the output of the delay element, and the outputs The bits through the zero decoder are connected to the control input of the BANCH element, which connects the input of the multiplier to the input of the first summing counter. 2 Il. (L

Description

one

The invention relates to computing technology and can be used in constructing arithmetic devices of digital computers in control and processing units for information designed to sum the pulses arriving at their inputs while simultaneously multiplying their sum by an integer factor equal to nine.

The purpose of the invention is to increase the speed of the relationship in the case of multiplying the number of pulses by 9.

FIG. 1 shows a functional diagram of the multiplier of the number of pulses; in fig. 2 - timing charts that show the work of the multiplier.

The multiplier contains input 1, connected via delay element 2 to the counting input of decimal counter 3 and directly to the information input of the BANNER element 4, the control input of which is connected to the output of the decoder 5 zero, which inputs are connected to the outputs of the bits of the counter 3, and output connected to the counting input of the summarizing counter 6.1. Summing counters 6.1, ..., 6.p-1 are connected in series. The multiplier also contains outputs of 7.1, 7.2, .., 7.n bits.

FIG. 2 The following notation is accepted: a is a sequence of multiplied pulses on bus 1; b - the temporary location of the signal at the output of the decoder 5 code zero; in - the sequence of pulses that passed through the element BAN 4 to the input of the counter 6.1; (d) two impulses transmitted to the input of the next counter 6.2.

It is necessary to note the change of the number 91, where i is a natural series of positive integers (see table)

. .Lll.-l

91

254479

An analysis of this table shows that as the number increases by one, the digit in the unit of the number 9 decreases by one (the transition from

5 o

9 - reduction of binary de

ten

15

thirty

from the digit code of the number by one), and the digit in the decimal form of the number 9 either increases by one or remains unchanged, and remains unchanged when the O number has been written to the discharge digit of units before this change. the numbers 9 and the multiplier action is constructed.

In the initial state, all the counters 3, 6.1, 6.2, ..., 6.P-1 are reset. Since in the initial state in the counter 3 the number O is written, then

20, at the output of the decoder zero 5 (t in FIG. 2b), there is a control signal, with the result that the BAN 4 element is closed for input signals.

The first input signal (Fig. 2a),

25 arriving at input 1, is fed to delay element 2 and to the information input of prohibition element 4. Since in delay element 2 it is delayed by a time equal to its duration, then by the time the counter 3 begins to go from state O to state O, and Consequently, by the time the signal changes at the output of the decoder 5 zero, the signal at the input of the BANCH 4 element stops and the signal 6.1 does not receive a signal (t in Fig. 2b). At the time of completion of the transition of the counter 3 in the counters 3, 6.1, ..., 6.P-1 will be fixed

40 number 0 ... 09.

The second input signal (t in Fig. 2a), fed to input 1, passes through the element BAN 4 on. counting input counter 6.1 (t on

45 of FIG. 2c) and changes its state from 0 to 1, as well as after a delay in element 2, the delay enters the counter 3 and changes its state from 9 to 8, resulting in 50 counts 3, 6.1, ..., 6.P-1 the number 0 ... 18 will be fixed.

Further, the operation of the multiplier is carried out similarly. When the next tenth, twentieth, ..., 10.k-ro pulse arrives, the decoder 5 produces a zero (moments

35

th

-thirty

etc. in fig. 26) the prohibitory closing element 4,

discontinuing the very flow of pulses to counters 6,1, .. ,, 6.п-1.

Claims (1)

Invention Formula A multiplier of the number of pulses containing a delay element and decimal summing counters, the input of each of which is connected to the overflow output of the previous one, and the outputs of the bits are connected to the outputs of the higher bits of the multiplier, whose input is connected to the input of the delay element, which corresponds to . J MJjJLJLJJL five 44 f (/ g, / 1220 2230 32 PP {1 P PP PP PP PP PPPP PPL P, I I I Compiled by V. Berezkin Editor I. Casarda Tehred L. Serdyukova Proofreader L. Pilipenko Order 4721/52 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 in order to increase the speed in the case of multiplying the number of pulses by 9, it contains the BAN, decryptor zero and decimal subtraction counter, the input of which is connected to the output of the delay element, and the bit outputs - with the outputs of the lower multiplier and the inputs of the zero decoder The output of which is connected to the control input of the BANNER element, the information input of which is connected to the input of the multiplier, and the output to the input of the first decimal summing counter. Submarine I I