SU1259283A1 - Device for determining number of combinations - Google Patents

Abstract

The invention relates to computing and can be used in devices revolving combinatorial tasks related to the calculation of the number of combinations. The aim of the invention is to increase the speed of the device. The device contains a comparison unit 13, a division I8 unit, a multiplication unit 23, a subtraction unit 10, four registers 2.5, 20, 27, a counter 12, a clock generator 4, six delay elements 3.7, 8, 15, 22, 26 , ten blocks of elements And 6,9,11,14,16,17,19,21, 24,25 for transmitting information, start 1 input, inputs 29.30 and device output 28. 2 Il. (L

Description

The invention relates to computing technology.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the layout of the device; figure 2 - the timing diagram of his work.

The device contains input 1 start, register 2, delay element 3, generator 4 clock pulses, register 5, block 6 elements And, element 7 delay, element 8 delay, block 9 elements And, block 10 subtraction, block 11 elements And, counter 12 , comparison unit 13, AND block 14, delay element 15, AND block 6, And block 17, division block 18, AND block 19, register 20, And block 21, delay element 22, multiplication block 23, block 24 And elements, block 25 And elements, delay element 26, register 27, output 28 and inputs 29 and 30. devices.

To calculate the number of combinations of C from K, an iterative method is used, based on the calculation at each iteration up to n inclusive

(f; - 1) K - (, m - 1)

J

€ f1-,

the current state of the counter, and iteration, thus j,

P

P

one

K.i.liii)

i

where P is the sign of the product.

Before the device starts operation, a record is made in the register of 2 numbers, la K in binary code, with 3 fog kg +

. +, and in register 5 - the numbers in the Dual HH4HOM code (Jfog n + 1 m)

The operation of the device starts on the Start command, which is fed to the I start input. Under this command, the initial installation is made of the subtraction unit 10, the division unit 18, the multiplication unit 23, the counter 12 and the register 20 in the zero state, and

. in register 27, a one is written in binary code. At the same time, the Start signal via delay element 3, which provides a signal delay for the time required for the initial installation of the blocks

device starts a 4-clock pulse generator.

The next pulse from the generator 4 output goes to the counting input of counter 12, increasing its content by one (the first pulse sets its state to 1, and n - to the state equal to n), sets it to €) , Potin

The binary codes of the counter state code are fed to the inputs of a block of 16 elements AND, a block of 17 elements AND, and a block of 19 elements I.

At the same time, the clock pulse arrives at the inputs of the delay elements 7 and 8, respectively. The output signal from the element 7, which is delayed mainly by the response time of the counter 12, is simultaneously fed to the inputs of blocks 6, M, 9, and 17 of the elements AND and the input of the delay element 15, respectively. By this signal, the binary code of the AV number is in parallel fed from register 5 through block 9 of the elements AND to the input of block 13.-comparison, the second input of which receives the binary code of the current state of counter 12 through block 17 of the elements I. Block 15 produces, compare two binary numbers. If the numbers being compared are equal, then the comparison unit generates a signal, which, entering the stop input of generator 4, prohibits the generation of clock pulses. If the numbers are not equal, then the generator through the time determined by the period of the following clock pulses, forms the next pulse, and the operation of the device

goes on.

.

Let. Numbers are not equal. Then the code

The numbers from register 2 are fed through block 6 of the e-pins to the input of the block, 10 subtraction, to the second input of which the binary code of the previous iteration counter stored in register 20 on the first iteration O is stored, recorded during the initial installation of the device. Thus, at the output of the calculator, there are potentials corresponding to the binary code of the difference K - f-.j (at the first iteration of K-0). After the time determined by the delay time of the i-th clock pulse by the delay element 8, the binary status code of the counter I2 from its output through the block of 16 AND elements

register entry 20, where it is recorded. At the i -th and iteration, the pulse delayed on element 15, arriving at the corresponding inputs of blocks 14 and 19 of elements I, allows the number n - C ;, binary block code to pass through them, respectively (at the first iteration. K-0) and the code of the current state of the counter (at the first iteration 1) to the inputs of dividing unit 18. The division unit performs the calculation of the quotient

 , „P-Och

(at the first iteration -).

At the same time, the pulse from the output of the delay element 15 is fed to the input of the delay element 22, where it is delayed by the time determined mainly by the response time of the dividing unit. The signal from the output of the delay element is fed to the inputs of the blocks 21 and 24 of the elements AND and the input of the delay element 26, thereby allowing passage to the inputs of the multiplication unit 23 from the output of the binary code number divider

- about

. „

on the first iteration), and with

code number

exit register 27

 on the first iteration). Block

multiplying the mind operation; hackles two binary numbers, the result

„P-1, -g p hP-o.

tat which - f (1 - on

(-one

: t1

the first step) in binary code enters through the block of 25 elements AND, opened by a signal from the delay element 26, to the input of the register 27, where it is recorded and stored until the next operation step of the device.

On the n-th iteration of the calculation, a code is formed at the output of the counter 12. The j state corresponding to the C p number. As a result, the comparison unit at € n generates a signal which, Incoming generator 4, stops the formation of clock pulses with the second information inlet streams. At the same time, all actions described for (and iteration) will be performed on Iteratio n. In this way, in register 27 there will be accumulated in binary code the product

with n

equal to the number of combinations. from K to Claim, which can be removed at output 28 in a binary parallel code,

Claims (1)

5 claims A device for determining the number of combinations containing the first register, four blocks of AND elements, 0 delay elements, ex. so that, in order to improve speed, a subtraction unit, a division unit, a multiplication unit, a comparison unit, a counter, are introduced into it, 5, the second, third and fourth registers, a clock generator and six AND elements, the inputs of the first and second registers being the first and second inputs of setting the initial values of the device, the start input of which is connected to the installation inputs of the subtractor, dividing unit, block multiplying, the counter, the third and fourth registers and the first delay element, the output of which is connected to the trigger input of the clock generator, the stop input of which is connected to the output of the comparison unit, and the output n with the inputs of the second and third delay elements and with the counting input of the counter, the first inputs of the first and second blocks of elements And are connected respectively to the outputs of the bits of the first and second registers, the outputs of the first and third blocks of elements And are connected respectively to the first and second information inputs of the subtraction unit -. nor, the output of which is connected to the first inputs of the fourth block of elements And, the output of which is connected to the first information input of the division block, the output of the fifth block of elements And is connected to the information input of the third register, the outputs of the second and sixth blocks of elements And are connected respectively to the first and second B1 soda block comparison, the output of the seventh block of elements And so5 0 five the house of the division block whose output is connected to the first input of the eighth block of elements AND, whose output and output of the ninth block of elements AND are connected respectively to the first and second information inputs of the multiplication unit whose output is connected to the first input of the tenth the block of elements And whose output is connected to the information input of the fourth register, the output of which is connected to the output of the device and to the first input of the ninth block of elements And, the output of the third register is connected to the first input of the third block of elements And, the output of the counter is connected to the first input In addition, the neck of this and the seventh block of elements is And, the output of the second delay element is connected with the second inputs of the first, second, third and sixth blocks 1 -I CS J  26 Editor N.Luola Compiled by A. Zher.enov Tehred I. Khodanich Proofreader A.Zimokosov Order 5124/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, - Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 59283 And elements and with the input of the fourth delay element, the output of which is connected to the second inputs of the fourth and seventh blocks of the And elements and to the input of the fifth delay element, the output of which is connected to the second inputs of the eighth and ninth blocks of And elements and to the output of the sixth delay element the output of which is connected to the second input of the tenth block of elements And, the output of the third delay element is connected to the second input of the fifth block of elements I. FIG. 2