SU1234837A1 - Variable priority device with coding address - Google Patents

Abstract

The device is intended for use in computing to organize multiprogram work. The device is distinguished by increased speed due to a simultaneous analysis of the priority codes of various requests. The device provides the selection of the highest priority request from all those received for servicing in the computer, as well as the formation of the modified part of the address of the G I bbservice request service. The priority of each request is variable and is set using the priority code. 1 il. (On the next 4 00 co.

Description

The invention relates to computing and may be applied to a program interruption device.

The purpose of the invention is to increase speed.

The drawing shows a block diagram of the device.

The device contains a register of 1 requests, blocks of 2 elements -and, registers of priority 3, decoders 4, a group of elements OR 5, block 6 of priority, groups of 7 elements AND 8, a group of elements OR 9, block 10 of priority, expander 11, element OR 12, Tr igger 13 element OR 14.

The device works as follows.

In the initial state, trigger 13 is set to O, priority codes are received in priority registers 3, and requests from subscribers are received in register 1.

The operation of the device starts at the Start signal, which arrives at the input through the element OR 14 and sets the trigger 13 into one state. The inputs of the decoders 4 receive codes only from those priority registers 3 for which there are requests in register 1. Using the OR 5 elements, signals from decoder outputs 4 of the same name 4 that have the same priority codes are combined into groups. The priority of the group is determined by the priority block 6, the output of which generates a signal corresponding to the group of requests with the highest priority. This signal opens the corresponding group of 7 elements And 8, to the outputs of which the signal of the most priority group of requests passes. Then, through the OR 9 elements, these signals are posted to the input of block 10, which determines the priority of requests within the group of requests with the same priority codes. At the output of block 10, the position code of the priority request number is generated.

Using the encoder 11, this code is converted into a binary one, which can be used as a modifiable part of the request service program address. At the same time, the selected signal sets the corresponding register register 1 in O, removes the serviced request from the queue, and also sets the trigger 13 through O via the IL 12 element.

Upon arrival of the signal, answer the input, the device operation cycle is repeated.

If the same priority codes are set for all or a number of subscribers, then a sequential service of requests is provided, starting with the higher bit of the register of requests.

As blocks 6 and 10, parallel action priority devices can be used.

Claims (1)

Invention Formula A variable priority device with address encryption, containing a register of requests, whose inputs are the device's request inputs, a trigger, an encoder whose outputs are a group of information outputs of the device, characterized by that. that, in order to increase speed due to simultaneous analysis of priority codes, the device contains (priority registers, where n is the number of sources of requests, a group of and decoders, a group of AND blocks, two groups of 1 SHI elements, two priority blocks 5, two OR elements and (t1 groups of elements AND (m is the number of priority codes), with the first input of each block of elements AND of a group connected to the output of the corresponding priority register, the second inputs of all blocks of elements of the AND group are connected by the Q output of a trigger, the group of outputs to A block of an element of the AND group is connected to a group of inputs of the corresponding group decipher, (—and output (where 1 1, 1Т) of each group decoder is connected to the corresponding input of the i -th element OR of the first group and the first inputs of the elements AND i -and groups, the output of each element OR of the first group is connected to the input of the first priority block, the 1st code of which is connected to the second input of the AND elements; the group 1 output of the | th element AND (where i 1, n) i-and ( j 1, m) of the group is connected to the -th input of the ith element OR of the second group, the output of which is connected to iJ; the input of the second priority block, the output group of which is connected to the group of inputs of the encoder, the group of inputs for resetting the register of requests and the group of inputs of the first OR element, the output of which is connected to the installation input; 1 which is connected to the output of the second OR element, the first and second inputs of which are the input of the response signal and the device Start input, respectively, with the third 5 priority codes of the device. the inputs of each block of elements And the group are connected to the output of the corresponding priority register, the inputs of the priority registers are connected to the group of inputs Compiled by V. Mikutsky Tehred M. Khodanych Circulation 671 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader E. Roshko Subscription