SU1242949A1 - Priority device for servicing interrogations in arrival order - Google Patents

Abstract

The invention relates to computing technology. The purpose of the invention is to increase the speed of the device. The device contains a request register, two groups of AND elements, two OR elements, a group of priority registers, a group of comparison circuits, a control trigger, request inputs, control inputs and outputs. New in the device is the introduction of a group of decoders, a third group of AND elements, a group of OR elements, an encoder and their links in the device, which ensures the achievement of the objective of the invention. 1 il., 1 tab. with blib IvO; about 4ik. WITH

Description

The invention relates to computing technology, in particular, to priority request processing devices,.

The aim of the invention is to improve the speed of the device.

The drawing shows a functional diagram of the device.

The device contains a register of 1 requests, a group of priority registers 2, a group of comparison circuits 3, a first group of elements AND 4, a second group of elements AND 5, a group of decoders 6, a group of E-mails OR 7, a third group of elements AND 8, an encoder 9, a control trigger 10 , the first 11 and the second 12 elements OR, the inputs 13 of the device requests, the inputs 14 of the device priority code, the outputs 15 of the device,

From the analysis of the data in the table it can be seen that the output number of the decoder uniquely corresponds to the value of the number and, moreover, the order of servicing the requests can be determined by sequential selection of the values of the numbers from the outputs of the decoders, i.e. The order of service for subscribers is as follows:. four .

 To analyze the priority codes, the same outputs of the decoders 6 are combined with the elements of OR 7, the output of which forms the following position code: 11101. This code is converted by AND 8 elements included in the priority circuit into the position code 10000 supplied to the encoder 9, the output of which the binary code for the number a is generated. In the group of schemes 3 in comparison with: the ignal is formed at the output of the scheme

input 16 signal Start and input 17, the response signal.

The device works as follows,

The initial state of the device is characterized by the fact that the registers 1 and 2 and the trigger 10 are set to the zero state (not shown), and the requests to the register 1 on the inputs 14. arrive synchronously ..

Let the number of subscribers and priority codes be set for each subscriber, with the highest priority subscriber corresponding to the lowest value of the priority code, i.e. a, 3, a,,.

If there are requests in register 1, the binary codes of these numbers are sent to the corresponding decoders 6, the work of which is reflected in the table.

40

Jj, where the full match of the codes occurs.

The operation of the device starts at the Start signal, inputted at input 16, through the element OR 12 to the single input of the trigger 10. By the single state; the trigger 10 opens the AND 4 elements and at the output of the AND element 4. A single cp1 signal is generated that enters the input 15j device. At the same time, this signal is set to O through the element OR 11 trigger 10 and the second register bit 1.

Since the elements AND 5 are closed, a binary code of a number is formed on the output of the encoder 9. From "G55 cash to element 4" is generated upon the arrival of a response signal from the subscriber arriving at the input 17 to the installation of 1 flip-flop 10.

If, after receiving the priority codes and signal, the Start into the 1 request register is not received, signals are not output at the device output, and the device is in the waiting mode. Upon the first incoming request, a signal is generated at the output 15 of the device, similarly to that described.

Claims (1)

Invention Formula A priority device for servicing; live requests in the order of arrival, containing the request register, the first and second groups of AND elements, the first and second OR elements, a group of priority registers, a group of comparison circuits, a control trigger, whose direct input is connected to the output of the first HnH element, whose inputs are the device inputs, and the inverted control trigger input is connected to the output of the first OR element, whose inputs are connected to the outputs of the corresponding AND elements of the first group whose outputs are outputs stroystva and reset inputs of respective bits of the register request, information WMOs rows which are inputs requests the device and connection request register outputs corresponding to the first inputs of the AND first grztpy and the control inputs of the respective AND gates of the second group of registers inputs a priority group are the device priority code inputs, the outputs of the group priority registers are connected to the first inputs of the corresponding circuits. 5 groups, the outputs of which are connected to the second inputs of the corresponding AND elements of the first group, characterized in that, in order to improve speed, the device contains 0 a group of decoders, a group of OR elements, a third group of AND elements and an encoder whose outputs are connected to the second inputs of the group comparison circuits, the outputs of the priority priority registers 5 connected to the information inputs of the corresponding elements And the second group, the outputs of which are connected to the inputs of the corresponding decoders group, the j-th output of every 7th Q decoder group where (g 1, 2, ..., h; j lj 2, ..., m; n is the number of subscribers; w- number of priority register bits) is connected to the i-th input of the j-th element of the ShZh group, the output of the first element OR of the group is connected to the first input of the encoder and to the first-inverse inputs of the AND elements of the third group, the output of the -th element OR group (where S 2,3, ..., tn) is connected to the direct input (5 -) - th and 5 th inverse input from the S-th to ("of the T-th elements of the third group, the output - The third element of the third group (where 1, 2, ..., t-1) is connected to the (p + 1) input of the encoder, the direct output of the control trigger is connected to the third inputs of the elements of the first group. 0 five