SU1352487A2 - Multichannel priority device - Google Patents

Abstract

The invention relates to digital computing, in particular, to priority devices, and can be used to process service requests from several active devices. Purpose of the image //; shadow is to increase the speed of the device by providing a minimum service time for all possible transitions of group requests. The device contains three registers 1, 2, 10, two triggers 3, 4, the element OR NOT 5, the control unit 6, the delay element 7, the request memory block 8 (ROM), the decoder 9. The device can be promptly excluded from further Arbitration serviced applications provide prompt support for group requests not only in cases of transitions to higher-priority requests, but also in cases of transitions to lower-priority requests. 1 ill., 1 tab. with S (L with SP 1chE 4 00 vj N

Description

The invention relates to digital computing, in particular, to priority devices, and can be used to process service requests from several active devices.

The purpose of the invention is to increase the speed by providing a minimum service time for all possible group transitions.

The drawing shows a functional diagram of the proposed multi-channel priority device for three channels,

The table shows the programming circuit of the request memory block (ROM), which is included in its composition. Accepted that the priority of the channel decreases with increasing its sequence number. In the table, the following notation is used: A; - state of j-ro bit

ROM addresses; And - the state of the j-ro bit information ROM; And, - is the jth highest priority channel (request).

The device (Fig. 1) contains the first 1 and second 2 registers, triggers 3 and 4, the element OR-NOT 5, the control block 6, 3jjeMeHT 7 delays, the block 8 in the query unit (ROM) with the address inputs of the least significant bits and additional address inputs of higher bits, decoder 9, register 10, request inputs 11, device outputs 12, synchronization input 13.

Table continuation

The essence of the invention is as follows.

In the device, the ROM is programmed in such a way that the state of its information outputs is determined not only by the state of the address inputs specified from the request inputs, but also by the state of additional

address inputs specified from the device outputs, except for the output of the least priority channel. At the same time, by the address inputs from the ROM, a code is selected that corresponds to the most priority of the requests placed on the request inputs, and taking into account the additional address inputs - the code corresponding to the highest priority request, i.e. without

accounting request placed at the entrance of a busy channel.

The active unit, the nsgrimer processor, initiating the exchange with the public device, when there is no permission signal associated with it, generates a request signal, which is in the form of a logical unit fed to the corresponding input 11 of the device. After receiving some

time, the resolution signal in the form of a logical unit from the output 12 of the device, the active device, without taking the request signal, exchanges the public device and

the end of the exchange. removes the request In response to the removal of the request signal from input 1, the device removes the enable signal from the corresponding output 12, the device then analyzes the accumulated requests, issues a permit for one of the outputs 12 to connect the next active device to the public device, and .d

In the absence of requests (the same state is outgoing), registers 1 and 2 are set to zero and logical zero levels are maintained at device outputs 12. In this case, the element OR-PC 5 forms a single signal supporting the decoder 9 in the open state. At the address inputs of the lower bits (from the outputs of the register 1) and at the address inputs of the A and J of the higher bits (from the outputs of the register 2) ROM 8, the logic zero signals are set. At the same time, the information outputs of the ROM are in the 00 o state. Under the action of the clock pulses acting on the input 13 (via the delay element 7), the register 10 is also set to the state 00

wherein at the outputs of the decoder 9, jr. request on another channel, for example on

connected with the corresponding synchronizing inputs of register 2, the levels of logical zero are maintained, since code combination 00 is not permitted for any of these outputs.

When a request is received for one of the inputs 11, for example, the input 11.2 of the second channel, register 1 is set to state 010 under the action of the next clock pulse at input 13. This same clock pulse delayed by the response time of register 1 and ROM 8 using element 7 delay sets the register 10 to the state 10, corresponding to the new state of the information outputs of the ROM 8 when its address inputs are 00010. The code 10 is decoded by the decoder 9 and at the synchronization input of the trigger 4 of the second bit of the register 2 appears nal logical unit that sets a eg.o 1. logitretemu signal, under the action of the next clock pulse at input 13, the register I is set in state 110, state variable younger

25 bits of the address of the ROM 8. In this case, the state of the higher bits of the address of the ROM 8 does not change and corresponds to the exchange permission set for the second poNry channel, i.e. full address ROM 8

3Q is of the form iOllO. This address at the output of ROM 8 corresponds to the next request on the third channel. In this case, the priority of the next request is lower than the priority of the request of the occupied channel, despite this after unlocking the decoder 9 (after removing the request from input P.2) in register 10 code 11 will already be prepared corresponding to the choice of the next request on the third channel and register 2 with a minimum delay equal to the response time of the output stage of the decoder 9 and trigger 4, will change its state to 100, setting

35

40

unit output 12.2 register-. the permission for the exchange on the third car 2 is a signal of authorization on the bank. Similarly, the proposed device handles requests for all possible group exchange transitions with a public device for a processor that has established a request at input 11.2. The same resolution signal through the element OR NOT blocks the decoder 9, the outputs of which in this case are supported by logic zero signals. In addition, a change in the state of register 2 leads to a change in the state of the address inputs of ROM-8 to state 10010, in which the information output of ROM 8 confirms state 10, corresponding to the choice of the second channel 50

55

out requests,

formula of invention

Multi-channel priority device - auth. SB, no. 1180895, characterized in that, with the Purpose of improving performance by ensuring a minimum service time for all possible group request transitions, the outputs are

la After the exchange is completed, the processor removes the request from output 11.2 and the next pulse at input 13 zeroes the register, which leads to an immediate (accurate to the trigger time 4) reset of the register 2, cleared by resolution from output 12.2 of the device and unlocking the decoder 9. Similarly, the proposed device serves any of the one-time requests,

When serviced 1-5 and group requests, the proposed device works as follows

If during the processing of one of the requests, for example, a request on the second channel, the additional charge will be

the third, then under the action of the next clock pulse at input 13, register I is set to state 110, changing the state of the lower

5 bits of the address of the ROM 8. In this case, the state of the higher bits of the address of the ROM 8 does not change and corresponds to the exchange permission set for the second channel, i.e. full address ROM 8

Q is of the form iOllO. This address at the output of ROM 8 corresponds to the next request via the third channel. In this case, the priority of the next request is lower than the priority of the request of the occupied channel, despite this after unlocking the decoder 9 (after removing the request from input P.2) in register 10 will already be prepared Code 11 corresponding to the choice of the next request on the third channel and register 2 with the minimum delay equal to the response time of the output stage of the decoder 9 and trigger 4, will change its state to 100, setting

five

0

50

55

out requests,

formula of invention

Multi-channel priority device - auth. SB, no. 1180895, characterized in that, with the Purpose of improving performance by ensuring a minimum service time for all possible group request transitions, the outputs are set to 513524876

All but the output, with the least priority, with the additional address input channel, are connected by the corresponding block of the request memory.

Claims (1)

Multichannel priority device - by ed. St., No. 1180895, characterized in that, in order to improve performance by ensuring a minimum service time for all possible transitions of group requests, the device outputs, except for the output of the lowest priority with additional addresses on the external channel, are connected by the corresponding request memory block.