SU1149258A1 - Multichannel device for servicing interrogations - Google Patents

Abstract

MULTI-CHANNEL DEVICE FOR SERVICE OF INQUIRIES, containing input and output registers, decoder, element OR-NOT, two elements OR, in each canape except the first and last, 2 I (where ti is the number of requests) elements AND, 2n elements IL, in the first channel - 2m of elements AND, c of elements OR, and in the last channel - 2p elements of AND, 2 ft of elements OR and c of elements NOT, with each request input of the device connected to the corresponding information input of the input register, the reset inputs of the device connected to the reset inputs of the input register and with the inputs of the first element OR, the outputs of the output register are informational outputs of the device and connected to the inputs of the OR element NOT whose output is connected to the first input of the second OR element, the second input of which is the device mode input, the output of the second OR element connected to the clock the input of the output register, each output of the input register is connected to the first inputs of the elements AND the first pair of the channel of the same name, the output of the first element OR of the last channel is connected via the first element NOT to the second inputs MI of the second elements And its and previous channels, the outputs of the odd elements of RSHI, starting from the third, last channel are connected to the first inputs of the even elements And, starting from the fourth, their own and previous channels, the output of the odd element And each channel is connected to the first input of the odd element of the same name OR of the next channel, the second inputs of odd elements OR channels, starting from the second one, are connected to the outputs of odd elements, And its channels' elements, (L the outputs of each pair of elements And channels, starting from the second, are connected to the inputs of even elements OR of their channels, the inputs of the elements OR of the first channel are connected to the outputs of the same pairs of elements AND of the first channel, the output of the i-element of the OR element of the first channel (.,. n) is connected to per4; vym and second eqs, respectively, 4D of the first and second elements And the i-th to U1 eo pair of its channel, the output of the j-ro even element of the ШШ channels, starting from the second (J - 2.4 ...), is connected to the first and second inputs respectively, the first and second elements AND the 5th pair of their channel, the output of the last element OR of each channel is connected to the same name information input of the output register, the output of the second element OR is connected to the output input of the output register, characterized in that, in order to expand the functionality of the device about rga

Description

In order to maximize the probability of full service, in each channel it contains a priority counter, each output of the channel priority counter connected to the second input of the odd element And starting from the first, own channel, the group of code inputs of the device is connected to the groups of information inputs of the priority counters

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thetates of all channels, the input of the recording of the priority count of each channel is connected to the decoder's output of the same name, the counting input

The priority priority j of each channel is the corresponding clock input of the device, the group of address inputs of the device is connected to the group of inputs of the decoder.

The invention relates to computing technology, in particular, devices for servicing requests, and can be used in the construction of computer systems and information exchange systems.

A device for servicing requests contains a distributor, a decoder, an input element OR, a shaper of groups of output elements AND, a group of registers, groups of input elements AND, a group of elements OR, triggers of requests, elements AND, OR and NOT T.

The drawback of the device is that it does not take into account the duration of processing requests.

The closest to the invention in technical essence and the achieved result is a device for priority control, containing an input register, channels, output register, element SH-NOT, element OR, decoder, and the channels contain priority registers, elements AND, elements OR, elements NOT 2 .

A disadvantage of the known device is that it does not allow changing priorities with regard to the intensity of service requirements, and this reduces the functionality of the device.

The purpose of the invention is to expand the functionality by organizing an order maximizing the likelihood of full service.

The goal is achieved by the fact that the device for servicing requests contains input and (output registers, decoder, OR-NOT element, two OR elements, in each channel, except the first and last, 2n (where n is the number of queries) of elements And, 2n elements OR, in the first channel - 2n elements AND,, n elements ISH, in the last channel 2n elements AND, 2n elements OR and

n elements are NOT, with each request input device connected to the corresponding information input of the input register, the device reset inputs are connected to the reset inputs

the input register and the outputs of the first element OR, the outputs of the output register are informational outputs of the device and connected to the inputs of the OR element NOT, the output of which is connected to the first input of the second OR element, the second input of which is the input of the device mode, the output of the second OR element with the clock input of the output register, each output of the input register is connected to the first inputs of the elements AND the first pair of the channel of the same name, the output of the first element OR of the last channel is connected through

 the first element is NOT with the second inputs of the second elements AND of its own and previous channels, the output of odd elements OR, starting with the third, last channel connected to the first inputs of even elements AND, starting with the fourth, its own and previous channels, the output of the odd element AND of each channel is connected to the first input of the odd element OR of the next channel, the second inputs of the odd elements of the OR channels, starting from the second are connected to the outputs of the odd elements AND their channels, the outputs of each pair of Icanal elements, beginning on the second, connected to the inputs of even elements OR of its channels, the inputs of the elements OR of the first channel are connected to the outputs of the same pair of elements AND of the first channel, the output of the i-element of the OR element of the first channel (... n) is connected to the first and second inputs of the first and the second element AND the 1st pair of its channel, the output of the j-ro even element of the OR channel, starting from the second (J 2,4 ...), is connected to the first and second inputs of the first and second elements, respectively And the j and pair of its channel output pseudo element OR of each channel is connected to The information input of the output register, the second OR element is connected to the reset input of the output register, a priority counter is inserted in each channel, each output of the channel priority counter is connected to the second input of the odd element And, starting with the first, own channel, the device code input group is connected to groups of information inputs of the priority counters of all channels, the input of the recording of the priority counter of each channel is connected to the decoder's output of the same name, the counting input of the counter priorities of each channel is a respective clock input of the device, the group of address inputs of the device connected to the group of decoder inputs.

The drawing is a block diagram of the device.

A device with a win, input register 1 with triggers 1.1 ... 1 .p, channels 2.1 ... 2.p, output register 3, element IPI-NOT 4, elements OR 5 and 6, decoder 7, request inputs 8.1. ..8.P devices, reset inputs 9.1 ... 9.P devices, address inputs 10 devices, code inputs 11 devices, outputs 12 devices, device mode inputs 13, clock inputs 14.1 ... 1A devices, counter 15 priorities, elements AND 16, elements OR 17, elements NOT 18.

The device works as follows.

After switching on, all subscribers need to assign priorities, which are assigned based on previous estimates of processing time made by the device during operation. The priorities of subscribers are determined by the priority numbers, the codes of which are entered into the counters of 15 priorities. The highest priority subscriber has the highest priority binary code. The elements AND 16, OR 17, NOT 18 provide the choice of the code priority from the subscribers who sent signals to register 1. Register 3 records the priority request.

The priority setting mode is performed in the following manner. The subscriber code is supplied to the inputs 10 of the decoder 7, and the subscriber's priority code is fed to the inputs I. The unit potential at the corresponding output of the decoder 7 enters the resolution of recording information on the corresponding information inputs of the corresponding counter .15. Thus, the priority codes of all subscribers are entered. The arrival of requirements on one or several inputs 8 of input register 1, for example, inputs 8.1 and 8.2, sets the triggers 1.1 and 1.2 to one state. We assume that the priority of the second subscriber is higher than the first (i.e., the binary code recorded in the counter 15 of the second 2.2 channel, less than the binary code recorded in the counter 15 of the first channel (2.1).

Further, elements AND 16, OR 17, NOT 18 channels provide the selection of the priority subscriber (priority code) - in this case the second one. A single signal from the output of channel 2.2 sets the second bit of output register 3 (at the synchronous input output register 3 is a single signal), which in turn is a subscriber service enable signal. The byte count of incoming requests is generated by the counter 15 at input 14.2 and is fed to the count input counter. After completion of a call, for example, 8 bytes in length, the request is removed (by a reset signal on input 9.2) of the second subscriber. In the counter 15 of the second channel 2.2 a code is written (lOOO + Nj), where N., the code originally recorded in the counter of the second channel. The device is then ready to serve the next requirement. Similarly, the assignment of priorities to other subscribers. Priority levels are waved after determining the service time as a result of counting the number of bytes when servicing a subscriber. It should be borne in mind that if the service byte period is different for different subscribers, then when determining service times, it is necessary to count not the number of bytes, but reference frequency cycles. In the future, the device serves subscribers, depending on the priority level assignment. The mode of setting relative and absolute priorities is performed using the control level, which is located at input 13. 1 86 When servicing with relative priority, the transition to serving the next demand is made only at the end of the current time required to service the demand of not the highest priority. With absolute priority service, the requests belonging to the highest priority queue are serviced at any time. If the input level 13 is zero, then the device operates in relative priority mode, if the positive level - in absolute priority mode. The application of the invention allows to expand the functionality of the device.

Claims (2)

MULTI-CHANNEL DEVICE FOR SERVICE OF REQUESTS, containing input and output registers, decoder, OR-HE element, two OR elements, in each channel, except for the first and last, 2 I) (where h is the number of requests) AND elements, 2 η OR elements, in the first channel - 2n AND elements, h elements OR, and in the last channel - 2n AND elements, 2 x OR elements and η elements NOT, each requesting input of the device being connected to the corresponding information input of the input register, the reset inputs of the device are connected to the reset inputs of the input register and the inputs of the first OR element, the outputs of the output register are information outputs of the device and are connected with the inputs of the OR-NOT element, the output of which is connected to the first input of the second OR element, the second input of which is the input of the device mode, the output of the second OR element is connected to the clock input of the output register, each output is input. the register is connected to the first inputs of the AND elements of the first pair of the same channel, the output of the first OR element of the last channel is connected via the first element NOT to the second inputs of the second AND elements of its own and the previous channels, the outputs of the odd OR elements, starting from the third, last channel are connected to the first inputs of the even And elements, starting from the fourth, its own and previous channels, the output of the odd element And of each channel is connected to the first input of the same odd element OR of the next channel, the second inputs of the odd elements of the OR channels, starting from the second. connected to the outputs β of the odd elements AND of their channels, the outputs of each pair of elements AND channels, starting from the second, connected to the inputs of the even elements OR of their channels, the inputs of the OR elements of the first channel are connected to the outputs of the same pairs of AND elements of the first channel, the output of the x-th OR element of the first channel (i “1 ... n) is connected to the first and second inputs of the first and second elements AND of the i-th pair of its channel, respectively, the j-ro output of the even element of OR channels, starting from second (j - 2,4 ...), connected to the first and by the second inputs of the first and second elements AND of the jth pair of their channel, the output of the last OR element of each channel is connected to the same input information of the output register, the output of the second OR element is connected to the reset input of the output register, characterized in that, in order to expand the functionality device by organizing the sequence, maximizing the probability of full service, it contains a priority counter in each channel, and each output of the channel priority counter is connected n with the second input of the odd element AND _> starting from the first channel, the group of code inputs of the device is connected to the groups of information inputs of the priority counters of all channels, the recording permission input of the priority counter of each channel is connected to the decoder output of the same name, the counting input of the priority counter of each channel is corresponding clock input of the device, the group of address inputs of the device is connected to the group of inputs of the decoder.