SU1070552A1 - Priority control device - Google Patents

Abstract

A DEVICE FOR PRIORITY CONTROL, containing input and output registers and element ORINE, and in each channel, except for the first priority register, 2p elements AND, 2n elements OR and n elements NOT, and in the first channel 2n elements I, yy n - the number of requests priority register, n elements OR and n NOT elements, with each device request input connected to the corresponding information input input register, device reset inputs connected to the input and output register reset inputs, input register outputs and formational outputs are devices and are connected to the inputs of the OR-NOT element, outputs of registers, priority of channels are connected to the first inputs of nonlinear elements AND their channels, the outputs of odd elements OR of the last channel are connected through corresponding elements NOT to the first 1 and inputs of even elements AND their own and previous ones channels, the output of the odd element AND of each channel is connected to the first input of the odd element OR of the next channel, the second inputs of the odd elements OR channels, starting from the second, are connected to the outputs not even elements AND their own channels, the outputs of each pair (t-th and (i + l) -ro) elements AND channels, starting from the second, are connected to the inputs of the even elements OR of their channels, the inputs of the elements OR of the first channel are connected. with the outputs of the same pairs of elements AND of the first channel, the outputs of the OR elements of the first channel and even elements of the remaining channels are connected to the second inputs of the pairs of elements AND their channels, starting from the second pair, the outputs of the last elements OR of all channels are connected to the D-inputs of the triggers The corresponding bits of the output register, characterized in that, in order to expand the field of application of the device, it contains a decoder and an OR element, and each output of the decoder is connected to the C inputs of the priority register The C-inputs of the output register triggers are connected to the output of the element OR, the first, second inputs of which are connected to the output of the element ILINE and the device polling input, the group of address inputs of the device are connected to the input group of the decoder, the group of code inputs of the device connected to groups of information inputs of the priority registers of all channels, each output of the input register is connected to the second inputs of elements AND of the first pair of the channel of the same name.

Description

The invention relates to computing and can be used to prioritize the maintenance of objects in control systems.

Priority device is known containing 11e registers, groups of elements AND, counters, pulse generator, triggers, elements OR 13.

However, such a device cannot be used to control the maintenance of objects with relative or absolute priority.

A multichannel priority device is known, containing an OR-NOT element, input and output registers-, channels, in each channel priority registers of channels, AND elements, OR elements, NOT elements, OR-NOT element, the information inputs of the device being connected to information inputs of the output register The inputs of which are connected to the first inputs of elements AND groups, the second inputs of which are connected to the output of the element OR NOT, the inputs of which are connected to the outputs of the output register, the information inputs of which are connected to the outputs Anal, output register unit outputs are outputs channel inputs connected to the outputs of the AND Group 2

The disadvantage of this device is the inability to process requests with relative and absolute priorities.

The purpose of the invention is to expand the scope.

The goal is achieved by the fact that the device for priority control contains input and output registers and an OR-NOT element, and in each channel except the first priority register, 2g elements AND, 2n elements OR, and n elements NOT, and in the first channel 2n elements And, where n is the number of requests, the priority register, n elements OR and n elements, NOT, each device request input with the corresponding information input of the input register, device reset inputs connected to the input and output register reset inputs, outputs in one register are informational outputs of the device and are connected to the inputs of the element OR NOT, the outputs of the channels priority registers are connected to the first inputs of the odd elements AND of their channels, the outputs of the odd elements OR of the last channel are connected through the corresponding elements NOT, to the first inputs of the even elements AND their previous channels, the output of an odd element And each

the channel is connected to the first input of the odd element OR of the next channel, the second inputs of the odd elements OR channels, starting from the second one are connected to the outputs of the odd elements AND their channels, the outputs of each pair of (1st and (1 + 1)) elements AND channels, beginning with the second is connected to the inputs of even elements OR their

0. channels, the inputs of the elements OR of the first channel are connected to the outputs of the same pairs of elements AND of the first channel, the outputs of the elements OR of the first channel and even elements OR pc5 of the current channels are connected to the second inputs of the pairs of elements AND of their channels, starting with the second pair, the outputs of the last elements OR of all channels are connected by cD -inputs of the triggers of the corresponding bits of the output register, the decoder and the OR element are entered, each decoder output connected to the C inputs of the priority register of the same channel, C inputs of trigger the output register is connected to the output of the OR element, the first, the second inputs of which are connected respectively to the output of the OR element and the device polling input, the device’s address input group is connected to the decoder input group, the device code input group is connected to the priority information registers of all channels, each output

5 input register is connected to the second inputs of the first pair of elements And the same channel.

Fig, 1 shows the structures. On the diagram of the device; in fig. 2 Q specific channel option.

The device (Fig, 1) contains the input register 1 (triggers 1., 1, 1.2,.,., L.h), channels 2 .1,2. 2,. . . , 2. П, output register 3 (triggers 3.1, 3.2 ,,., ,, 3. п), element OR NOT 4, element OR 5, decoder b, query inputs 7.1,7.2, ..., 7.m devices , inputs 8.1, 8.2, .. ,, 8.p device reset, address inputs 9.1, 9.2 .., 9. 1 device code

0 inputs 10.1, 10.2, ..., 10. devices, information outputs 11.1, 11.2 ,,,, 1l.h devices, interrogation input 12 devices, channels 2.1, 2.2,.,., 2.11 contain registers 13

5 priority, elements AND 14, elements OR 15, elements NOT 16.

When service is required, the objects send requests from inputs. 7.1, 7.2, ...,

0 7.P to the corresponding RAPR of the input register 1. To the inputs 7.1,7,2,.,., 7.p, sensors of the start of service of objects are connected, to the inputs 8.1,8.2, .., 8.p. - end sensors facilities servicing, and to outputs 11.1,11.2, ..., 11.n - executive bodies of serviced facilities. The number of bits in registers 1 and 3 is equal to the number of objects. I give signals for wok at random times. The priority of the objects is determined with priority numbers, the codes of which are entered into the priority registers 13 of the objects of the modules of the priority object allocation unit. The highest priority (binary) code corresponds to the highest priority object. When the system is running, these codes may change during each priority assignment cycle in the system. Element groups AND 14, OR 15, NOT 16 provide the selection of the priority code from the objects that sent signals to the register. Triggers of the output register 3 fix the priority request. The device can operate in three modes. 1. The priority setting mode. The inputs 9.1, 9.2 ...., 9.V are given the object code, and the inputs 10.1 10.2, ..., 10. - priority code of the object. Next, the decoder b excites the output, the number of which coincides with the object number and enters the synchronization inputs of the triggers of the priority register of the corresponding channel, and the information inputs of the triggers of the priority register of 13 receives the priority code of the given object. Thus, the priority codes of the objects are entered into the corresponding priority registers of all the serviced objects; submitting to inputs 9.1, 9.2, ..., 9.1 is the object code, and at inputs 10.1, 10.2, ..., 10.1 is the object's priority code. 2. Service management with relative priority. A signal O is applied to the interrogation input 12. Upon receipt of requests for inputs 7.1,7.2, ..., 7.1 are set to i, respectively. The corresponding triggers of input register 1, channels 2 (according to the specified priorities) allocate priority to the object. A single signal from the output of the corresponding channel 2 sets the corresponding trigger of the output register 3 (a single signal on the output register sync.), Which in turn is the object service disconnect signal. By setting the output register 3 to the i trigger, the output register is locked, i.e. through the element OR-NOT 4, the output of which is connected to the second by the input of the element OR 5, is applied to the synchronous inputs of the trigger register of the output register 3. When the signal after this signal comes from an object with a higher service priority, the information input of the corresponding trigger of the output register 3 is set to WitsH, however, O on the synchronous input prohibits the passage of a signal for servicing an object with the highest priority. At the end of the service of an object with a lower priority, the corresponding input 8 receives a signal to terminate the service of the object and the corresponding triggers of the input 1 and output 3 registers are reset. Resetting the corresponding trigger of the output register 3 causes the appearance. unit potential at the synchronization input of the triggers of the output register 3, which will allow to maintain the object with high priority. Thus, the maintenance of any object is not interrupted, and when the software finishes its maintenance, maintenance of the object with the highest priority begins. . 3. Manage maintenance of objects with absolute priority. Input 12 is signaled. When requests are received for inputs 7.1,7.2, ..., 7.), The corresponding triggers of input register 2 are set to 1, then channels 2 are assigned to the priority object. A single signal from the output of the corresponding channel 2 establishes the corresponding trigger of the output register 3. Then, at the output of the OR-NOT 4 element, an O signal appears, but presence at the input. 12 signal 1 does not block syi; The trigger output trigger register 3. When a signal is received from an object with a high priority, the outputs of channels 2 change, i.e. At the output of the channel, 2 appears corresponding to the object with the highest priority, and at the remaining outputs the signal O Next, the corresponding trigger of the output register 3 is set to H and the object with a higher priority starts to be serviced, and the maintenance of the object with a lower priority is interrupted. At the end of the servicing of an object with a higher priority, the corresponding input 8 receives a signal for the termination of servicing the object. In this case, the corresponding trigger of the output register 3, whose service has been interrupted, is again set to 1. Next, an object with a lower priority starts to be serviced. The invention allows to expand the field of application of the device.

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J.2 12

7l 8.P

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Claims (1)

DEVICE FOR PRIORITY MANAGEMENT, containing input and output registers and an element ILINE, and in each channel, except for the first, priority register, 2 η elements AND, 2η elements OR and η elements NOT, and in the first channel 2 η elements AND, where η - the number of requests, priority register, η elements OR and η elements NOT, with each request input of the device connected to the corresponding information input of the input register, the reset inputs of the device connected to the reset inputs of the input and output registers, the outputs of the input register are information the ion outputs of the device are connected to the inputs of the OR-HE element, the outputs of the registers, the priority of the channels are connected to the first inputs of the non-linear elements AND their channels, the outputs of the odd elements OR of the last channel are connected via the corresponding elements NOT to the first inputs of the even elements of both their own and previous channels, the output of the odd AND element of each channel is connected to the first input of the odd OR element of the next channel, the second inputs of the odd elements OR channels, starting from the second, are connected to the outputs of the odd elements in And of its channels, the outputs of each pair (n'th and (i + l) -ro) of elements And channels, starting from the second, are connected to the inputs of even elements OR of their channels, the inputs of OR elements of the first channel are connected to the outputs of the same pairs elements AND of the first channel, the outputs of the elements OR of the first channel and even elements OR of the remaining channels are connected to the second inputs of the pairs of elements AND of their channels, starting from the second pair, the outputs of the last elements OR of all channels are connected to the D inputs of the triggers of the corresponding bits of the output register, which differs those that, in order to expand the scope of the device, it contains a decoder and an OR element, with each decoder output connected to the C-inputs of the priority register of the same channel, the C-inputs of the output register triggers connected to the output of the OR element, the first, second inputs of which are connected respectively with the output of the ORINE element and the polling input of the device, the group of address inputs of the device is connected to the group of inputs of the decoder, the group of code inputs of the device is connected to the groups of information inputs of the registers prioritize and all the channels, each output of the input register is coupled to second inputs of AND gates of the first pair odnoimen Nogo channel.