SU1737449A1 - Priority device - Google Patents

Abstract

The invention relates to computing and can be used in computing systems. The purpose of the invention is to expand the scope of application by allowing the organization of service requests at low intensity of their arrival. The device contains five registers, three groups of elements AND, two blocks of elements I. four elements OR, an element of prohibition, a shift register, two blocks of elements OR, two triggers, four elements AND, a comparison circuit, four delay elements, a pulse shaper and an element NOT . The operation cycle of the device consists in periodic review of the demand and their acceptance for servicing in accordance with the priority codes assigned to them, 1 sludge.

Description

The invention relates to computing and can be used in computing systems.

A device of cyclic priority, containing four registers, four groups of AND elements, OR elements, a prohibition element, a ring shift register, a trigger, a group of delay elements, and a pulse shaper, is known.

The disadvantage of the device is narrow scope.

The closest to the proposed is a priority device, containing five registers, three groups of AND elements, two AND blocks, four OR elements, a forbidding element, a shift register, two OR elements, a trigger, three AND elements, a comparison circuit, two elements delay, pulse shaper and the item is NOT.

The disadvantage of this device is a narrow field of application, since

weak intensity of requests are possible cases when at the time of termination of the service of the subscriber the next request in the first register is not found. In these cases, the priority code of the served application remains in the second register. Therefore, when another application with a lower priority is received for a free service channel, this application is not accepted for service. In the device, the received applications are viewed until a application with a priority greater than that of the last served application is found.

The purpose of the invention is to improve the performance of the device.

The goal is achieved by the fact that the priority device contains five registers, three groups of AND elements, two blocks of AND elements, four OR elements, an NOT element, a prohibition element, the first and third AND elements, two blocks of OR elements, form (L

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pulse world, the first and second delay elements, the comparison circuit and the first trigger, the request inputs and the device service end inputs are connected respectively to the single and zero inputs of the first register, the single outputs of which are connected to the group of information inputs of the first block of elements AND whose outputs are connected to the unit inputs of the second register, the unit output of each bit of which is connected to the first input of the homonymous element AND of the first group, the second input of which is connected to the same name The output of the shift register, the outputs of the elements AND of the first group are connected to the inputs of the first element OR and the information inputs of the second block of elements AND whose outputs are connected to the single inputs of the third register, whose single outputs are connected to the outputs of the device, the unit output of each bit the third register and the output of each element And the first group is connected to the control input of the same subgroup of elements AND, respectively, the third and fourth groups, the information outputs of which are connected to the outputs of one group of bits of the fourth register, and the inputs of which are connected to the inputs of the device priority codes, the output of the first element OR is connected to the input of the element NOT, the first input of the first element AND, and the inverse input of the prohibition element, the direct input of which is connected to the clock input device, and the output is connected to the control input of the first block of elements And and. the control input of the shift register, the device's fault input is connected to the first input of the second element AND, the second input of which is connected to the output of the element NOT, and the output to the first input of the second element OR, the output of which is connected to the control input of the second block of elements AND, the outputs of the elements And, the second and third groups are connected to the inputs of the first and second blocks of the OR elements, respectively, the outputs of which are connected respectively to the information inputs of the fifth register and the first group of information inputs of the comparison circuit, the second and the group of information inputs of which is connected to the outputs of the fifth register, the output of the pulse former through the fifth delay element is connected to the interrogation input of the circuit compared to 1, the outputs Equals More and Less than which are connected to the first inputs of the third element, And the third and fourth elements, respectively OR, enable and disable interrupt outputs of the device are connected respectively to the single and zero inputs of the first trigger, the single output of which is connected to the second input of the third element AND, whose output is one with the second input of the third OR element, the output of which is connected to the input of the second delay element and the second input of the second OR element, the third input of which is connected to the output of the first And element, the output of the second delay element is connected to the second input of the fourth OR element, the output of which is connected to the input reset the second register, entered the second trigger, the fourth element And, the third and fourth delay elements, and the device's fault input is connected to the single input of the second trigger, the unit and zero outputs of which It is connected respectively to the second input of the first element AND and the first input of the fourth OR element, and the output to the pulse driver input, the output of the first AND element is connected to the input of the third delay element, the output of which is connected to the second input of the fourth OR element and the fourth delay element input , the output of which is connected to the zero input of the second trigger1.

The drawing shows the scheme of the proposed device priority.

The device contains registers 1-5, groups of 6-8 elements AND, blocks 9 and 10 elements AND, elements OR 11-14, element 15 prohibition, register 16 shift, blocks OR 17 and 18, triggers 19 and 20, elements AND 21- 24, comparison circuit 25, delay elements 26-29, pulse generator 30, HE 31, clock input 32, reset input 33, enable and disable interrupt inputs 34 and 35, respectively, request inputs 36, service end inputs 37, priority inputs 38 and exits 39.

A conventional device for comparing binary numbers is used as the comparison circuit 25.

The device works as follows.

When the power is turned on, registers 1-3 are zeroed out, subscriber priority codes are entered into the corresponding groups of bits 4 of register 4 (higher priority corresponds to a smaller code), one of bits of register 16 is set to one, and the remaining bits Register 1 b - to zero. Initial installation circuits are not shown in the drawing. The trigger 19, depending on the permission or the prohibition of dialing, for subscribers with the same priority codes is set to one or zero state by the corresponding inputs 34 and 35. The trigger 20 by input 33 is set to one, which corresponds to the free service channel,

After that, the input 32 starts to receive clock pulses. They pass through an open zero level from the output of the OR 11 element of the prohibition element 15 and shift the unit in register 16 around the ring. Requests from subscribers arrive at inputs 36 and are written to the corresponding bits of register 1, and after the next clock pulse arrives at the input of block 9, the elements And are written to the corresponding bits of register 2.

If at the moment there are units in the bits of registers 2 and 16, then a single level appears at the output of the corresponding element And 6. The element OR 11 is triggered, as a result of which the prohibition element 15 closes, temporarily stopping the shift of the contents of the register 16. At the same time, the trigger 20 is set to one state (after the initial installation later), then the element 22 triggers, from which the signal through the element AND 12 is fed to the control input of the AND unit 10, as a result of the operation of which a unit is written to the corresponding register bit 3 of the register. At output 39, a signal appears enabling the subscriber to establish a connection with the serving device (shared resource). Service begins. The unit level from the output of register 3 passes to the input of the corresponding group of 7 elements AND, recording the priority code of the subscriber serviced from the corresponding group of register bits 4 through the block 17 elements OR to register 5. After the time required to record information in register 3, the delay element 28 connected to the output of the element 22 is triggered, the signal from the output of which passes through the element OR 14 and zeroes the register 2. This results in the removal of the single potential from the output of the element AND 6, the element OR 11 and open element 15 of the ban. The unit shift in register 16 begins again and the next service request is searched. The first regular clock pulse shifts the contents of register 16 and searches for the next service request. The first regular clock pulse is to shift the contents of register 16 and copy the information from register 1 to register 2 (frequency

clock pulses and time delays of operation of elements AND block 9 and triggers register 2 must be selected so that the information from register 1 is rewritten into register 2 after the contents of register 16 are shifted 16). After the time required for the high potential to be removed from the output of the OR 11 element, the delay element 29 connected to the output of the delay element 28 is activated, with the result that the trigger 20 is set to the zero state. If at the moment when element 6 triggers, trigger 20 is in the zero state (the servicing device is occupied), element 24 is triggered, a high level from the output of which is fed to the input of the pulse shaper 30 a signal from the output of which is fed to the input of the delay element 27. After the time required for the receipt of the priority code found in the request register (B) from the corresponding group of register bits 4 through the group of elements AND 8 and the group of elements OR 18 to the inputs of the comparison circuit 25, as well as the comparison of this code with those stored in register 5 code (A), the delay element 27 is triggered. As a result of polling the comparison circuit 25, a signal appears at one of its outputs. Three cases are possible: A B, A B and A B.

If A B, then the element OR 13 is triggered, from the output of which the signal is fed to the input of the element OR 12. After this, the delay element 26 is triggered, from the output of which the signal is fed to the input of the element OR 14. As a result, the request will be interrupted.

If A B, the found request is ignored, since its priority is lower than the priority of the currently served subscriber. Triggering an element OR 14 leads to resetting register 2 and continuing polling. Since this request is not served, after the next shift in register 16, it (among other requests) is rewritten to register 1 to register 2,

If A B, depending on the state of the trigger 19, either an ongoing maintenance interrupt (AND 23, OR 13, etc.) is triggered, or the device is placed in a waiting state for service to end.

If the service is completed before the next request is found, an input is sent to the input 33, according to which the trigger 20 is set to one, and the element 21 is triggered, from which the signal passes through the element

OR 12 to the control input of the block 10 of the elements AND, reset register 3. In addition, the corresponding trigger of register 1 is set to the zero state by input 37.

If the service ends when the device is in the idle state, the signal at input 33 causes the trigger 20 to become one, as a result of which element 22 is triggered, the output of which produces the described actions.

In the future, the device works similarly.

Claims (1)

The invention The priority device containing the shift register, five registers, three groups of elements AND, two blocks of elements AND, four elements OR, element NOT, an element of prohibition, three elements AND, two blocks of elements OR, a pulse driver, two delay elements, a circuit comparison and the first trigger, with the request inputs and the service end inputs of the device connected respectively to the single and zero inputs of the bits of the first register, the single outputs of the bits of which are connected to the group of information inputs of the first b Loka elements And whose outputs are connected to the single inputs of the bits of the second register, the single output of each bit of which is connected to the first input of the element of the same name And the first group, the second input of which is connected to the same output of the shift register, the outputs of the elements of the first group are connected to the inputs of the OR element and the information inputs of the second block of AND elements, the outputs of which are connected to the single inputs of the bits of the third register, the single outputs of the bits of which are connected to the outputs of the device, the unit output of each bit of the third register and the output of each element of the first group are connected to the first inputs of like elements of the second and third groups of the same name, the second inputs of which are connected to the outputs of like bits of the fourth register, the single inputs of which are connected to the inputs of device priority codes, output the first element OR is connected to the input of the element NOT, the first input of the first element AND and the inverse input of the prohibition element, the direct input of which is connected to the clock input devices, and the input is from the control inputs of the first block of the AND elements and the shift register, the device’s fault input is connected to the first input of the second And element, the second input of which is connected to the output of the element NOT, and the output to the first input of the second element OR, the output of which is connected to the control input of the second block of elements AND, the outputs of the elements AND the second and the third group is connected to the inputs of the first and second blocks of the OR elements, respectively, the outputs of which are connected respectively to the information inputs of the fifth register and the first group of information inputs of the comparison circuit, the second group of information inputs of which are connected to the outputs of the fifth register, the output of the pulse former through the first delay element connected to polling the input of the comparison circuit, the outputs Equal To, More and Less than which are connected to the first inputs of the third element AND, the third and fourth elements OR, the enable and disable inputs interrupts of the device are connected respectively to the single and zero inputs of the first trigger, the single output of which is connected to the second input of the third element I, the output of which is connected to the second the input of the third OR element, the output of which is connected to the input of the second delay element and the second input of the second OR element, the third input of which is connected to the output of the first AND element, the output of the second the delay element is connected to the second input of the fourth OR element, the output of which is connected to the reset input of the second register, characterized in that, in order to improve the performance of the device, a second trigger, a fourth And element, a third and fourth delay elements, and a device reset input are introduced into it connected to the single input of the second trigger, the single and zero outputs of which are connected respectively to the second input of the first element And and the first input of the fourth element And, the second input of which is connected to the output th first OR gate, and the output - to an input pulse generator, the output of the first element AND is connected to the input of the third delay element, the output of which is connected to the second input of the fourth OR element and the input of the fourth delay element, the output of which is connected to the zero input of the second trigger.