SU1341640A1 - Interruption signal forming device - Google Patents

Abstract

The invention relates to automatics, computing and computing, and can be used in the design of computing systems. The purpose of the invention is to increase the speed by reducing the response time to a request of lower priority after servicing a shutdown over-o20 s (L 00 4 05 4

Description

high priority. The device for generating interrupt signals contains a register of 1 interruption, a register 2 of a peripheral device, n prohibition elements 3 (n is the number of device request inputs), n-1 elements OR 4, multiplexer 5, a generator of 6 pulses, the first - third triggers 7- 9, tO decoder, prior1

The invention relates to automation and computing and can be used in the design of computing systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional scheme of the device.

The device contains the interrupt register 1 with outputs 1.1-1.p, register 2 of the interrupter device code, prohibition group 3.1-З.п, OR elements 4.1-4. (P-1), multiplexer 5, generator of 6 pulses with the first - third outputs 6..3, the first - the third trigger 7-9, the decoder 10 with the first - nth outputs 10.1-IO.n, the priority encoder 11, the first - the third elements And 12-14, the element OR-NOT 15, the input 16 of the cyclic device polling, device readiness input 17, device fault 18 inputs, peripheral device code output 19, device interrupt signal output 20.

The priority encoder 11 is used to form the peripheral device code requiring interruptions, which currently has the highest priority, and can be performed, for example, on the basis of the K 580 IV 165 chip. For example, the correspondence table describing the operation of the encoder 11 has the following form.

Input Signals O 001

1. Output signals

About 1

ABOUT

About 1

ABOUT

1 o

the tether encoder 11, the first is the third element AND 12-14, the element OR NOT 15, the device allows to reduce the response time to a request of a lower priority after serving a higher priority interrupt and can operate both in the polling priority mode and in the cyclic mode survey, 1 Il., 1 tab.

Table continuation

q q.

Input Signals Output Signals

The device for treating crashes can operate in the following modes: priority polling; cyclical survey. In the priority poll mode on

input 16 no signal. The generator 6 generates at the outputs 6.1-6.3 a sequence of pulses T 1, T 2 and T 3. The first pulse of the sequence T1 confirms the zero state of the trigger 8, and the trigger 7 goes into the single state, so

as the D input last from input 17 receives a signal. In addition, the register 1 from the inputs 18 records the interrupt signals that go to the information inputs of the multiplexer 5 and to the first inputs of the prohibition elements 3.1-Z.p (the signal from the output 1.1. Of the register 1 goes to the first input of the prohibition element 3.1, etc. .).

Since after switching on the device all its memory elements (triggers 7, 8, and 9 and registers 1 and 2) are in the zero state, after the first pulse of the T1 sequence (if there is a signal at input 17), the trigger 7 goes to the single state and in register 1 interrupt requests are written. The signals from the outputs of register 1 corresponding to peripheral devices requiring processor faults at the current time, through open on the second input, the corresponding prohibition elements 3.1-З.п are fed to the priority encoder 11. For example, if third and fifth peripheral devices require service , then in the 3rd and 5th bits of register 1 are recorded single signals, which, through the elements

prohibitions 3.3 and 3.5 are received on cipher-30 are absent). Since the trigger 7 is a torus 11. The encoder 11 at its outputs generates the code of the peripheral device with the highest priority, which requires that the device be interrupted at the current moment. During the interrupt processing process, the device operates as follows. The interrupting device, which the processor starts servicing, removes the interrupt signal from the device inputs 18. When pulses of the T 1 sequence are received, register 1 records interrupt signals from peripheral devices and triggers 7 and 8 go to the zero state (signals at inputs 16 and 17

is in the zero state, then the pulses of the sequences T 2, TZ are not received at the outputs of the elements 12 and 13. At the output 20, the signal of the processor (for the considered application 35 output 19 information

In accordance with the table at the output of the encoder 11, a code 011 is formed). From the output of the encoder 11, the code goes to the D-inputs of the register 2 and to the inputs of the element OR NOT 15.40

Upon receipt from output 6.2 of the generator 6 of the first pulse of the sequence T2, an pulse appears at the output of the element 12. This pulse is fed to the trigger synchronization input of trigger 9 and confirms the zero state of the latter (the zero signal arrives at the D input of trigger 9).

Upon receipt of output 6.3 of the generator 6 of the first pulse of the sequence of the TZ, a pulse opens at the falling edge of the T3 output element. At the same time, the code of the peripheral device with the highest priority is written to register 2 from the outputs of the encoder 11 requiring perryshan. From the outputs of register 2, the code goes to output 19 of the device

O

0 are missing). Since trigger 7

va, to the control input of the multiplexer 5 and to the decoder 10. At the same time, the interrupt request signal from the peripheral device with the highest priority from the corresponding output 1.i of register 1 through the multiplexer 5 enters the output 20 of the device.

For the example considered above, the register 2 records the code 011, and the signal from the output 1.3 of the register 1 enters through the multiplexer 5 to the output 20 of the device. After receiving the interrupt signal from the device output 20, and the code of the interrupting peripheral device from output 19, the processor removes the ready signal from the device input 17 and proceeds to processing the signal.

During interrupt processing, the device operates as follows. The interrupting device, which the processor starts servicing, removes the interrupt signal from the device inputs 18. When pulses of the T 1 sequence are received, register 1 records interrupt signals from peripheral devices and triggers 7 and 8 go to the zero state (signals at inputs 16 and 17

is in the zero state, then the pulses of the sequences T 2, TZ are not received at the outputs of the elements 12 and 13. At output 20, a signal from 0

five

0

five

about

five

does not change.

After the interrupt processing, the processor issues a ready signal to the processing of the next interrupts to the input 17. Upon receipt of the next pulse sequence T1, the trigger 7 goes into one state and the device proceeds to process the next interrupt from the peripheral device having the highest priority at the current time.

In the absence of interrupt signals from peripheral devices at the output of the encoder 11, and consequently, at the outputs 19 and 20 of the device, there are no signals.

In the cyclic polling mode, the device operates as follows. When the processor is ready for servicing breaks, inputs 16 and 17 receive signals of processor readiness for servicing interrupts.

When the first pulse of the T1 sequence arrives, the generator 6 triggers 7 and 8 go to one state, flip-flop 9 goes to the zero state, and register 1 records interrupt signals from peripheral devices (for example, from the first, fifth and seventh devices) .

Since the trigger 9 is in the zero state before starting this mode, a single signal appears at the output of AND 14. In this case, the decoder 10 opens the control input control. The signals from the output of the decoder 10 are closed on the second input of the elements of the ban 3.J-3.1 (j peripheral device code recorded in register 2). The signals from the outputs 1.1-1..P of the register 1 through the elements of the prohibition 3 (j + 1) - Z.p arrive at the inputs of the encoder 11. At the output of the encoder 11, the code of the peripheral device with the highest priority is generated (for the considered example it is the first device, Register 2 is recorded with a zero code) and code 001. Next, the device, when servicing the request, functions similarly to the algorithm specified by Bbmie. Upon receipt of the next pulse of the TZ sequence, code 001 is written to register 2. -The device then functions similarly to the indicated algorithm for the priority polling mode. Upon receipt from the processor of the Readiness Signal at input 17, the device proceeds with the maintenance of the next peripheral device (for the example under consideration, code 101 is generated similarly to the indicated algorithm at the output 19 of the device).

After servicing the processor from the peripheral device by the processor, the proposed device can serve the alarm from devices whose priority is lower, since the interrupt signals from the first to the fifth device in the cyclic polling mode are masked by prohibition elements 3.1-3.5 and are not received by the encoder 11.

For the example in question, the interrupt from the seventh device is serviced as follows.

After servicing the peripheral device with the lowest priority, signals at the input of the encoder 11 are absent. At the same time, the sequential impulse of the sequence T2 triggers 9 to a single state. In this case, the signal at the output of the element I 14 disappears and there are no signals at the outputs of the deflector 10. Elements of the prohibition 3.1-Z.p otkryshayut- with the second inputs. In this case, the encoder 11 receives signals from outputs 1.1-1.P of register 1. On the next pulse of the sequence T 3, register 2 records the code of the peripheral device, which needs to be interrupted and has

time is the highest priority. Further in this mode, the device functions in the same way as the specified algorithm.

If it is necessary to process several interrupts from the same peripheral device, then the output 20 of the device from register 1 constantly receives an interrupt signal until it is serviced. The processor sends a ready signal to the device input 17 only in the absence of a signal at the device output 20.

Claims (1)

Invention Formula An apparatus for generating interrupt signals comprising a first and the second triggers, pulse generator, decoder, the first - the third elements And, the polling multiplexer, interrupt register, and the interrupt inputs of the device are connected to the corresponding inputs of the interrupt register, the outputs of which are connected to the information input of the polling multiplexer, the device ready input is connected to the D input of the first trigger the output of which is connected to the first inputs of the first and second elements I, the cyclic polling input of the device is connected to the D input of the second trigger, the output of which is connected to the first input of the third element I, the first and second outputs of the pulse generator are connected to the second inputs of the first and second elements, respectively, different the fact that, in order to improve speed, the peripheral device code register, the third trigger, a group of prohibition elements, the priority encoder, the first through (n-1) -th OR element (n is the number of outgoing requests), the OR element NO, the third output of the pulse generator is connected to the synchronization inputs of the interrupt register, the first and second triggers, the R-BXO is the third trigger house, the i-th output of the alarms register (, n) is connected to the information input of the i-ro group prohibition element, the output group which is connected to the group in The priority of the encoder, whose output group is connected to the input group of the OR-NOT element, and to the group of information inputs of the peripheral code register, the output group of which is connected to the output group of the peripheral code, and the group of information inputs of the decoder, whose j-th output is (, (( n-1) 20 interrupt register is connected to connected to the first input by the j-ro element of the information inputs of the ILT multi-pin, the output of the first OR element of the plexer, the group of code inputs is connected to the control character of the first t Oogo is connected to the group of outputs of the group inhibit element, the output of the K-th register of the peripheral device code of the OR element (, (p-1)) is connected to the gate. 416408 the second input (K-1) of the OR element and with the control input of the K-th element of the group prohibition, the p-th output of the decoder is connected to the second input (n-l) -ro 5 of the OR element and with the control input of the nth group inhibiting element, the output of the first element AND is connected to the synchronization input of the third trigger, the output of the second element AND is connected to the synchronization input of the peripheral device code register, the output of the OR element is NOT connected to the D input the third trigger, the inverse output of which is connected to the second input of the third 15 of the element And, the output of the third element And is connected to the control input of the decoder, the output of the interrogation multiplexer is the output of the interruption signal of the device, a group of outputs