SU1741133A1 - Priority device - Google Patents

Abstract

The invention relates to computing and can be used in control circuits for public devices. The aim of the invention is to improve speed. The device contains two groups of AND-NOT elements, two groups of AND elements, a group of triggers, five AND elements, an element of a NOT pulse generator, a trigger, a mask register and a mode register. In the device, the next request is recorded immediately after the end of the previous service, and the incoming request is serviced after the end of the service of higher priority requests and in the absence of their arrival. 1 ill., 1 tab.

Description

The invention relates to computing technology and can be used for the control of public devices.

Priority device known

The lack of which should be attributed to the independence of the time of service requests from their priority. The device has advanced functionality, but it does not provide the ability to change the priority of requests.

Closest to the proposed is an asynchronous device of variable priority.

However, this device has a number of drawbacks: the discipline of servicing requests is rigidly fixed, the recording of newly received service requests occurs only after servicing all previously recorded ones, which leads to a long waiting time for servicing high priority requests.

The aim of the invention is to expand the field of application of the device by providing the possibility of changing its operating modes.

The goal is achieved by the fact that in an asynchronous variable priority device containing the first group of NAND elements, the first group of AND elements, the trigger register group of the query register, the second group of NAND elements, the second AND group of elements, the first mask register, the first AND element, the element is NOT, the clock pulse generator, the second element is AND, the trigger, the third element is AND, the first input of which is connected simultaneously to the output of the first element AND, the input of the element NOT, to the input of the generator of clock pulses, the output of which is connected simultaneously to the first input of the third and second input of the second elements AND, the output of the second element AND is the output of the device, the request inputs of the first group of inputs of which are connected simultaneously by the first inputs of the corresponding 2

SO OE

The first and fourth groups of inputs whose outputs are connected to the first and fourth inputs of the same name triggers of the query register group, the second inputs of which are combined and connected to the bus logical zero of the device, and the third inputs are combined and are the first reset input of the device, the response inputs The second group of inputs of which are connected simultaneously to the second inputs of the NAND elements and the third inputs of the elements of the first groups, the second input of the device mask recording is connected simultaneously with the second input of the installation into one The trigger trigger and the first input of the first mask register, the group of information inputs of which is the third group of device inputs, and the outputs are connected simultaneously to the fourth inputs of the corresponding AND elements of the second group and the second inputs of the corresponding AND-NOT elements of the second group, the first inputs of which are connected simultaneously to the outputs of the corresponding triggers group triggers register requests and the first inputs of the corresponding elements And the second group, the third inputs of which are combined and connected to the output element and NOT, the fifth inputs of the second and third elements AND the second group are combined and connected simultaneously to the fourth input of the fourth element AND the second group, the second input of the first element Peak to the output of the first element AND-NOT of the second group, the sixth input of the third element 1/1 of the second group is connected at the same time to the third input of the first element AND, the output of the second element AND-NOT of the second group and the fifth input of the fourth element AND of the second group, the sixth input of which is connected simultaneously with the output of the third element AND-NOT of the second group and the fourth the first element AND whose first input is connected to the second inverse output of the fourth trigger of the request register trigger group, the first output of which is connected to the first input of the fourth element AND of the second group of AND elements whose outputs are a group of device outputs, the first element OR is additionally introduced the fourth AND element, the second OR element, the OR OR NOT element, the second mode register, the fifth AND element, the output of which is connected to the installation input to the state of the first mask register, the second input of the fifth AND element connected to the first trigger output, and the first to the second output of the second mode register, the group of information inputs of which form the fourth group of device inputs, the third

the input of which is connected simultaneously to the input of the recording of the second mode register and the second input of the OR-NOT elements, the output of which is connected to the second inputs of the AND elements of the second group, the first input of the OR-NO element is simultaneously connected to the output of the first OR element and the first input of the fourth AND element, the output of which is connected simultaneously to the output of the first OR element and the first input of the fourth AND element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the third AND element, output second

The 5th OR element is simultaneously connected to the second inputs of the NAND elements of the first group, the second input of the fourth element AND is connected to the first output of the second mode register, the inputs of the first element OR

0 are connected to the same inputs of responses from the second group of device inputs.

The drawing shows a diagram of the proposed device.

The device contains the first group

5 elements AND-NOT 1, the first group of elements AND 2, the group of triggers 3 query register, the second group of elements AND-NOT 4, the second group of elements AND 5, the first register 6 of the mask, the first element AND 7, the element

0 NOT 8, clock generator 9, second element AND 10, trigger 11, third element AND 12, first element OR 13, fourth element AND 14, second element OR 15, element OR-NOT 16, second reg5 of the 17 modes, n the second element 18, the first 19 and second 20 groups of inputs, the first 21 and second 22 input buses, the third 23 groups of inputs, the third 24 input bus, the fourth 25 groups of inputs, a group of outputs

0 26, the output bus 27.

The device works as follows.

In the static mode, the triggers and registers of the device are set to any position. In the dynamic mode, the operation of the device begins with the recording of the operating mode of the device and the mask. After power is turned on, the first input bus 21 enters the third inputs of the 3 group triggers.

0 signal setting triggers 3 groups in the zero state.

After that, the second 22 and third 24 input buses send recording signals to the first inputs of the first and second 17 registers, as a result of which the mask code present on the third group of inputs 23 is written into the first 6 mask register, with zero bits indicating masked priority levels present on the fourth group of inputs 25

the mode code is recorded in the second 17 mode register, and the trigger 11 is set to one. In accordance with the code recorded in the second 17 mode registers, the device can operate in four modes in accordance with the table.

Mode 1. Stage recording requests.

In this mode of discrete service of requests without using a mask in the initial state, the group of triggers 3 of the query register is reset, 00 is written in the second request register 17, the mask code is recorded in the first register 6 of the mask.

As a result, from the first output of the second register 17 of the mode a low level signal is fed to the second input of the fourth element AND 14, prohibiting the passage of signals through it from the output of the first element OR 13 to the first input of the second element OR 15. The low level signal from the second output of the second register 17 mode enters the first input of the fifth element And 18, prohibiting the passage through it of high-level signals from the first output of the trigger 11 to the second input of the first register 6 of the mask, with the result that the first register 6 of the mask turns out to be nnym in a high impedance state (hereinafter state) all the time on the device operation in this mode. Since the triggers of group 3 of the query register are set to zero, low level signals are present on their forward outputs, which are simultaneously received at the first inputs of the AND-HES 4 elements of the second group and the AND 5 elements of the second group, resulting in 26 outputs of the group of device outputs so there are low-level signals, and at the outputs of the N-elements of the second group there are high-level signals that go to the corresponding inputs of the first element AND 7. Since the first input of the first element And 7 also contains a signal high level, then the output of the first element And 7 also has a high level signal that arrives simultaneously at the element HE 8, a clock generator 9 and the first input of the third element And 12, as a result of which the output of the element HE 8 low signal goes to the third inputs of the elements of the 5th group of the second group, blocking them, the clock pulse generator starts to work, as a result of which a pulse is generated at its output, which causes the trigger 11 to the zero state. Since the output of the first element And 7 continues to be a high level signal, the pulse generator 9 produces the next pulse, which converts the trigger 11 into a single state, as a result

at the output of the third element And 12, a pulse is generated, coming from its output through the second element OR 15 to the second inputs of the AND-NE elements of the first group,

permitting the entry of the input request groups 19 to the triggers of the 3 groups of triggers of the query register, resulting in the triggers of the 3 groups of triggers of the query register being set to one state.

The high level signal from the output of the corresponding triggers of the 3rd group of triggers of the query register enters simultaneously the first inputs of the corresponding AND 5 elements of the second group and the I – E E 4 elements of the second group, from whose outputs the low level signal simultaneously arrives at the corresponding inputs of the II 5 elements of the second group and inputs of the first element And 7, as a result of which at the output of the first element And 7 there is a low level signal that will cause the clock generator 9 to stop and the signal will appear

low level at the output of the third element And 12, as a result of which the further recording of requests to the triggers of the 3 groups of triggers of the register of the requests is terminated. At this point, the recording of requests is completed.

The stage of processing requests.

The low level signal from the output of the first element And 7 is fed to the input element

HE 8, from the output of which the high level signal arrives at the third inputs of AND 5 elements of the second group, however, the high level signals coincide only at the inputs of that AND 5 element of the second group, which receives a high level signal from the output of the corresponding trigger of the 3 group of trigger registers. Thus, at the outputs of the 26th group, only one is present at any given time.

high level signal, and at that output 26 of the group of outputs, which corresponds to the highest unprocessed request. Upon completion of processing the request, a response impulse is received at the corresponding input 20 of the second group of inputs, which, after passing through the input of the corresponding trigger 3 of the trigger register group 3, resets it to the zero state. At the same time, the same impulse

comes through the first element OR 13 and the element IL AND-NOT 16 to the second inputs of the elements AND 5 of the second group, blocking the output of high-level signals for the duration of the response pulse. As a result, the high level signal is taken from the corresponding output 26 of the output group.

After a time different from the response pulse duration, similarly, a high level signal appears at the next output 26 of the output group of the device, if the corresponding trigger 3 of the trigger register group 3 of the request register is set to one.

Stage of the end of request processing.

After all requests of this group are processed, all inputs of the first element And 7 will have high-level signals (since all triggers of the 3 groups of trigger registers of the request register are set to zero), therefore, at the outputs of the corresponding AND-NOT 4 elements The second group contains a high level signal. As a result, at the output of the first element And 7, a high level signal is formed and the device starts a new cycle of operation.

Mode 2. Stage recording requests.

In mode 2 discrete servicing of requests using a mask, the initial state of the registers and triggers of the device, as well as their operation, is similar, except that a high level signal is present at the second output of the second register 17, allowing a signal from the first trigger output 11 As a result, by the time this phase ends, the first output of the trigger 11 contains a high level signal, which through the fifth element I 18 enters the second input of the first register 6 of the mask, Performan which the outputs of the first register mask 6, and therefore on the respective hodah AND-NO elements and the second group will be present mask, and low level signals would be masked prior match queries m priorities.

Request processing mode.

This stage takes place with the only difference that at the beginning of the service only unguarded requests. After all non-masked requests are processed, high level signals appear at all inputs of the first element And 7. From the output of this element, the high level signal is fed to the input of the clock pulse generator 9, which generates the next pulse, which triggers 11 to the zero state, resulting in a low level signal from the first output of the trigger 11 through the fifth element 18 to the second input of the first register 6 of the mask and translates it into a state, as a result of which the mask code is removed from the second elements AND-NOT 4 of the second group and the processing of requests that were previously masked begins.

Stage of the end of request processing. A characteristic feature of modes 1 and 2 is 5 discrete query service, i.e. The recording and maintenance of the next group of requests of different priorities is performed at certain points in time determined by the moment of the end10 or the processing of the last of the requests of the previous recorded group. Mode 3. Stage recording requests. In mode 3 of continuous servicing of requests without using a mask, the initial state of the triggers and device registers is the same, except that the first output of the second register 17 of the mode contains a high level signal allowing the passage of pulses from the output of the first element OR 13 through the fourth the element AND 14 and the second element OR 15 to the second inputs of the elements OR NOT 1 of the first group.

Stage recording requests. After processing the next request, the response pulse for the corresponding input 20 of the second group of inputs goes to the same input of the first element OR 13 and from its output through the fourth element AND 14 and the second element OR 15 to the second inputs of the AND-NOT elements of the first group, as a result which, in the corresponding triggers of the 3 groups of triggers of the query register, the queries will be recorded, if at this time they

5 are exposed at the corresponding inputs 19 of the first group of inputs. In this case, the request with the highest priority will be served, even if it has just arrived. To service requests of lower priorities, the device will go only if there are no requests with the highest priority at the moment. If at the time of servicing the request with a low priority a request with a higher priority is submitted, then it will be served immediately after the end of the service of the previous request . Stage of the end of request processing. In this mode, the end of request processing occurs if the request is no longer received. The device is in a standby state,

Mode 4. Stage recording requests.

5 This stage of the mode 4 of continuous service of requests using a mask is similar, but with the only difference that the use of the mask code mask recorded in the first register 6 is allowed.

The stage of processing requests.

After servicing all the recorded, unmasked requests, in the absence of newly received requests, trigger 11 is switched and the masked requests are serviced.

Stage of the end of request processing.

Thus, a feature of modes 3 and 4 is the continuous service of requests, i.e. the next request is recorded immediately after the end of the previous service, and the incoming request is serviced after the end of the service and the absence of incoming requests.

The use of the prototype device allows servicing incoming requests for one fixed service discipline, in which applications with the highest priority are forced to wait for the service to end to a group of requests with lower priorities. The use of the proposed device allows changing the discipline of service when changing the parameters of the request flow, which leads to an increase in the quality of service of requests with higher priorities.

Thus, the proposed device can be used in control units of common use devices with increased demands on the quality of service of requests with top priorities.

Claims (1)

Invention priority priority device containing two groups of AND-NOT elements, two groups of AND elements, trigger group, mask register, three 2I elements, NOT element, clock generator, trigger, first input of the first element AND connected to the output of the second element AND, input of the NOT element and the input of the clock generator, the output of which is connected to the first input of the third element I, the second input of the first element I and to the C input of the trigger, the recording input of the mask register is the recording input of the device and connected to the S input of the trigger the output of which is connected to the third input of the first element AND and the second input of the third element AND, the output of which is the output of enabling the recording of a device mask, a group of request inputs of which are connected to the first inputs of the same-name elements AND-NOT and AND first groups whose outputs are connected to S - and R-inputs, respectively, of the same name group triggers, the direct outputs of which are connected to the first inputs of the AND elements of the second group and to the first inputs of the same-name elements of the NAND of the second group, with the exception of the latter, the second inputs are connected to the same-named bit outputs of the mask register and to the second inputs of the elements of the same name of the second group, the third inputs of which are connected to the output of the NOT element, the outputs of the second group AND-NOT elements are connected to the corresponding inputs of the second element AND, the output i-ro (, ..., n - 1, n is the number of requests) of the AND-NOT element of the second group is connected to the corresponding inputs with (i +1) -ro on the n-th element of the second group, the outputs of the elements of the second group are the group of request outputs of the device, the input response group of which is connected to the second inputs of the AND and AND-NOT elements of the first groups, respectively, the D inputs of the group triggers are connected to the logical zero bus of the device, the C inputs of the group triggers are ticks th input device, the group the information entries of the mask register is a group of device mask inputs, characterized in that, in order to improve speed, the first OR element is additionally introduced into it, the fourth element is AND, the second element is OR, the element is IL-AND-NOT, the mode register, the fifth element is AND, the first input of which is connected to the first bit output of the mode register, the group of information inputs of which is a group of device mode inputs whose recording input is a group of inputs of the device mode whose recording input is connected to the record input of the mode register and the first input of the IL-AND-NOT element, the second input of which is connected to the output of the first OR element and the first input of the fourth AND element, the second input of which is connected to the second bit output of the mode register, the output the fourth element AND is connected to the first input of the second element OR, the second input of which is connected to the output of the first element AND, the single output of the trigger is connected to the second input of the fifth element AND, the output of which is connected to the mask register issue enable input, the output of the IL AND-IS element is connected to the fourth inputs of the AND elements of the second group, the input response group of the device is connected to the corresponding inputs of the first OR element, the output of the second OR element to the third inputs of the AND-NE elements first groups. S ; &