SU1487041A1 - Dynamic priority unit - Google Patents

Description

The invention relates to computing technology and can be used in computing systems. The invention relates to computing equipment and can be used in computer systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the proposed device.

The device contains a register of 1 requests, blocks of 2-5 elements AND, block 6 of mask memory, elements OR 7-10, shift register 11, clock generator 12 pulses, output register 13, delay elements 14 and 15, element 16, trigger 17, the decoder 18, the overwrite register 19, the block of elements OR 20, the group 21 of the device's request inputs, the group of 22 inputs of the device masks, the device's reset input 23, the installation input 24 of the device, the group of permitting outputs 25 of the device.

max The purpose of the invention is to increase the speed of the device. The device contains a query register, blocks of AND elements, a block of memory masks, OR elements, a shift register, a clock generator, delay elements, an AND element, a trigger, a decoder, an overwrite register, and a group of OR elements. The cycle of the device is a periodic review of the register of requests in accordance with the masks of priorities recorded in the corresponding block in descending order of priorities. The device has a service discipline with absolute priorities. 1 il.

The device works as follows.

When power is turned on in block 6, a group of inputs 22 enters an array of priority masks, impulses from input 24, registers 1 and 13 are reset, and register 11 is reset (the first digit is set to one, and the remaining digits are reset), trigger? set in the steering state.

The pulses from the output of the generator 12 are fed to the control input of the register 11, shifting the unit recorded in it along the ring. Requests from subscribers come in a group of 21 inputs and records ”· into register 1. For each pulse from the output of the generator 12, a unit is shifted in register 11 by one bit. The selection of masks from block 6 is controlled by information from the output

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Dov register 11. Another selected mask is fed to the second group of inputs of block 2 of the elements I. If the subscriber polled by this mask did not receive a request, then no signal appears on any of the outputs of block 2. In this case, the device waits for the next pulse from the output of the generator 12. If the subscriber polled with the next mask contains a request in register 1, then a signal appears at the corresponding output of the 2 AND unit that goes to the And 16 element. service of a subscriber, then at the output of the element OR 10 there will be a high potential and therefore the element AND 16 is triggered, with the result that the trigger 17 is set to one state, the contents of the register 13 through the block 4 elements And is found in register 19. The same signal with the delay necessary to perform the described operations (the required delay is provided by the element OR 8) resets the register 13 to the zero state. After that, a signal appears at the output of the element 15 delay. At the same time, the unit of register 13 corresponding to the subscriber selected for servicing is recorded in the unit, which is fed to the corresponding output 25, allowing communication of this subscriber with the server. In addition, there is a signal at the output of the element OR 9 and the register 11 is set to its original state.

The next pulse from the output of the generator 12 begins the search for requests from subscribers, whose priority is higher than the priority of the subscriber, the request from which is accepted for service. If a request from a higher priority subscriber is found, then it is accepted for service, and the processing of a request from a lower priority subscriber is temporarily suspended. If there is at least one application with interrupted service, trigger 17 will be in a single state, thereby preventing the operation of element 16 and preventing copying of the contents of register 13 to register 19. If there are no requests from a higher-priority source, then when selecting a mask from block 7, corresponding to the subscriber being served, the contents

Register 13 is confirmed and the search for requests from higher priority subscribers begins again.

At the end of servicing any request, a pulse is sent to input 23, which is used to selectively reset the serviced request in register 1, reset register 1 3 and reset the register to 11. At the same time, the number of requests from subscribers in register 1 is checked by the decoder 18 If there is a single request (the decoder 18 is triggered), and this is an application with interrupted service (trigger 17 is in the unit state), then after a delay time determined by delay element 14, atyvaet unit 5 and elements, the output of which the contents of register 19 via the OR group 20 elements is rewritten into register 13. Immediately begin service. At this time, the pulses from the generator 12 will be fed to the input of the register 11, searching for requests from higher-priority subscribers,

During the operation of the device, the priority of subscribers can be changed by entering in block 6 of the inputs 22 new masks.

Claims (1)

Claim A dynamic priority device containing a register of requests, the first and second blocks of AND elements, a mask memory block, three OR elements, a shift register, a clock generator, an output register and a first delay element, the group of device request inputs connected to the group of single inputs of the request register, the output group of which is connected to the first group of inputs of the AND block, the output group of which is connected to the group of information inputs of the second block of AND elements and the inputs of the first OR element, the output of which it is connected to the input of the first delay element and the first input of the second OR element, the output of which is connected to the control input of the output register, the output group of which is connected to the group of enabling outputs of the device and to the group of zero inputs of the query register, the control input of which is connected to the second input of the second OR element , a device reset input and the first input of the third OR element, the second input of which is connected to the installation input of the device, the set input of the query register and · the third input of the second element OR, the output of the third element OR is connected to the setup input of the shift register, the control input of which is connected to the output of the clock generator, the output register of the shift register is connected to the group of address inputs of the mask storage unit, the group of information inputs 15 is connected to the input group of device masks , the group of outputs of which is connected to the second group of inputs of the first block of elements I, the output of the first delay element is connected to the control input of the second block of elements And, and to the third input Another element is OR, which is distinct from the fact that, in order to increase the speed of the device, 25 the fourth element OR, the AND element, the trigger, the third and fourth blocks of the AND elements, the overwrite register, the decoder, the block of the OR elements and the second element are entered into it delays, with a group of outputs of the output register connected to information inputs. the third block of elements And with the input "1 6 On the fourth element OR, the output of which is connected to the first input of the element AND, the second input of which is connected to the output of the first element OR the third input of the element AND is connected to the zero output of the trigger, the output of the element. And is connected to the single input of the trigger block of elements And, the group of outputs of which is connected to the inputs of the rewriting register, the outputs of which are connected to the information inputs of the fourth block of elements And, the first control input of which is connected to the reset via the second delay element The device's input, the second control input of the fourth block of elements AND is connected to the direct output of the trigger, the group of outputs of the fourth block of elements AND is connected to the first group of inputs of the block of elements OR, the second group of inputs of which is connected to the group of outputs of the second block of elements And, the group of outputs of the block the OR elements are connected to the output register input group, the output register group is connected to the decoder inputs, the output of which is connected to the third control input of the fourth block of AND elements, is set input devices connected to the zero input of the flip-flop. 1487041