SU1246096A1 - Device for distributing jobs among processors - Google Patents

Abstract

The invention relates to computing and can be used. multiprocessor computing systems. The purpose of the invention is to increase the speed of the device when servicing the applications in a circular cyclic algorithm. New in the device is the use of six AND elements, the Three Triggers, a pulse generator, two delay elements, a group of prohibition elements, an encoder, an NOT element, a priority encoder, a comparison circuit and their connections in the device. 1 il. N3 NU Gfi O CO O5

Description

The invention relates to computing and can be used in multiprocessor computing systems.

The purpose of the invention is to increase the speed in the service mode of the application according to a circular cyclic algorithm.

The drawing shows a block diagram of the device.

The device contains a trigger 1 trigger, a device trigger input 2, a generator of 3 pulses, an AND 4 element, an AND 5 element, an AND 6 element, a delay element 7, a delay element 8, a mode trigger 9, control inputs 10 and 11 of the device mode, a trigger 12 shift control, comparison circuit 13, write trigger 14, element 15, element AND 16, element NOT 17, priority encoders 18 and 15, element AND 20, element And 21, trigger 22, trigger, element OR 23, elements OR 24 and 25 , group of elements And 26, element 27 of delay, element And 28, element H 29, switch 30, first control input 31 of switch 30, the second control input 32 of the switch 30, the first information input 33 of the switch 30, the second information input 34 of the switch 30, the first group of outputs 35 of the switch 30, the second group of outputs 36 of the switch 30, the group of storage registers 37, And block 38 39 AND elements, shift register 40, shift control input 41- shift register 40, shift register 40 reset input 40, group of information inputs 43 of shift register 40, reset group of inputs 44 of shift register 40, delay element 45, delay element 46, element group And 47, register 48 switchgear Events, device information output group 49, readiness register 50, And 51 group of devices, device information input group 52, buffer register 53, output 54 of the code of the number of processors of the buffer register 53, output 55 of the code of the task number of the buffer register 53 , a group of elements OR 56, an element AND 57, a single-vibrator 58, an element OR 59, a group of elements AND 60, a register 61 of readiness, a group of one-shot 62.

The device works as follows.

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The initial state of the device is characterized by the fact that the triggers 1, 14, 12 and 22, registers 40, 61, 53, 50 and 37 are set to the state O (not shown). Thereafter, inputs 52 to readiness register 50 are received. in the corresponding bits assigned to each processor, the readiness signals of the processors. At input 33, applications are received containing the code of the task number and the code of the number of processors required to solve it, accompanied by: and the trigger signal at input-2.

The operation of the device consists of two stages. At the first stage, a queue is formed from incoming orders at input 33 to switch 30 in the group of storage registers 37, the number of which is determined by the number of sources of the application. At the same time, the state of the processors is monitored at this stage. If the processor is free, the corresponding bit in register 50 is set to 1, and since the shift register 40 is in the zero state, then the output of the OR 23 element produces a zero signal, through which the AND 60 elements are opened through the HE 17 and OR 59 elements Here, the single ready signals, fixed in register 50, are transmitted to the corresponding bits of the ready register 61.

Queuing of quotes is carried out as follows. Since the shift register 40 is in the state O, the unit output signal of the NOT 17 is opened at the first inputs of the elements And 28 and 29 and the first element of the 26 group, and at the second input - the last element of the 26. As the trigger 14 is in O state, then through the third input

element 29 is open, and element 28 is closed by a zero signal from a single trigger output 14. By means of elements 28 and 29, a recording signal is generated, which provides

transfer by switch 30 to outputs 35 and 36 and further to the inputs of the first storage register 37, or the contents of buffer register 53 from input 34, or application from input 33, respectively. On the first impulse of the generator, coming through the open elements And 4 and And 26 and the element 27 of the delay on the second inputs of the elements And 26f and

31

29, the first application is recorded in the first register 37.

 Under the influence of clock signals in registers 37, a queue of applications for solving problems is formed as follows. The recorded in the first register 37 for clock pulses from the outputs of the corresponding elements And 26 is moved to the last register 37 of the group. For each successive clock pulse of writing to the first group storage register 37, a new application may be placed from the input 33 of the device as described. In this case, for the order, which is in the queue, the service discipline is implemented according to the algorithm First came - first served.

In the next clock cycle after the last register 37 is filled (the first application received), the second stage of the device operation begins.

Depending on the state of the trigger 9 mode, the device can operate in one of two modes: servicing the order in the order of arrival, or servicing the order according to a circular cyclic algorithm. The first mode corresponds to the unit state of trigger 9, which is set by the signal at input 11 of the device, and to the second, zero, which is set by the signal at input 10 of the device.

In service mode, in the order of arrival, a task can get the required number of processors to solve without waiting for the release of a sufficient number of processors if the device has the required number of free processors, and with waiting when they are assigned to the task as the processors release. The operation of the device in this mode is characterized by the combination of the functions of distribution and tracking of the state of the processors.

When servicing requests for a circular cyclic algorithm, first, an analysis is made of the possibility of assigning the required number of processors to a task from among those fixed at the time of distribution. In this case, if the number of free processors is less than the required ones, then the application returns to the end of the queue, and the next application enters the service. If the number of free processors is greater than or equal to the required one, then

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distribution with free processors for this task.

The operation of the device in the service mode in the order of arrival is as follows. The trigger 9 of the mode is set to state 1 by a signal on input 11, which enters the device after setting it to its initial state.

) 0 After filling the last register 37 of the group for the next clock signal from the output of the last element AND 26 code of the number of required processors from this register 5 through the open elements of the block 38

element And a single signal from the output of the element NOT 17 to the inputs 43 is transferred, tf to the shift register 40. After some time, determined by delay element 2720, the application from the last but one register is transmitted to the last register 37 of the group. The presence of a delay element 27 in the write control circuit in the last register 37 of group 25 allows for the completion of writing to registers 40 and 53 before the state of the queue changes, i.e. before the shift queued in the queue. From this, parameters of delay element 27 are selected. The delay element 46 provides a combination of the moments of occurrence of information at the outputs of the buffer register through the elements 38 and 39 and the clock signal from the output of the last element 11 of the group 26.

Thus, by the time the processor starts allocating the distribution function of the processors, the device is characterized by the following state.

Register 40 contains the code of the number of processors required for repenging the task, register 61 contains the position code of the state of the processors, register 53 contains the copies of the application selected for service, registers 37 queue requests for solving the tasks. Next, the device implements the distribution function of the processors to the selected task.

 After writing the code of the number of required processors in register 40 on the element OR 23, a single potential is established, which opens the second input elements AND 15, 16, 5 and 6, 55 through the first - AND element 20, with the Zero signal from the output of the HE element 17 at the same time, elements AND 29, elements AND 26 of the group and

40

45

blocks 38 and 39 of the elements AND, as well as a single signal at the first input of the element OR 59, is removed. But since the mode igger 9 is set to state 1, a single signal level is maintained at the output of the SHSh 59 element. At the same time, in register 61, the state of the processors is monitored, which is necessary for distributing processors to a task when the number of free processors is less than the required ones. A feature of the processor state tracking function is that the transfer of the processor from the idle state to the idle state can occur as a result of the execution of the processor allocation function to the task, and the release of the processor, i.e. its transfer from the state to the Free state can occur at any time of the device operation. After the information is transmitted to the shift register 40 with a single signal from the output of the OR element 23, the AND element 20 is opened and, after some time, determined by the delay element 45, is set to state 1 via the OR 25 element, the issue trigger 22. During the delay, the element 45 is determined by the duration of the transient processes in the AND 38 elements, in the shift source register 40, and the element 17. Therefore, the parameters of the delay element 45 are selected so that the pulse at the second input of the AND element 20 acts upon completion of the transient processes elements And 38, in register 40 and element 29.

By the zero signal from the output of the element NOT 17, the last element AND 26 and the element 29 are closed, thus blocking the reception from input 33. By the signal from the single output of the trigger 22, elements 51 are opened.

If, before the next clock signal of the generator of 3 pulses, the single signals in the corresponding AND 47 elements coincide, the corresponding bits of the distribution register 48 are set to state 1. The corresponding, one-shot 62 groups, the output signals of which set them to state About the corresponding bits of registers 50 and 40. At the same time through the open elements And 51 set

the corresponding register bits 50 are placed in the state O, and at outputs 49 the task number is transferred to the corresponding groups from register 53 by outputs 55. Thus, in the corresponding output groups 49, the corresponding processor is given a signal of its choice and task number to be solved, and in the ready register 50, the corresponding bit reflects the state of the processor Zan t.

In this case, two cases are possible: after setting the state O of the bits of the shift register 40, its total. the contents became zero, the values of 1 remained in one or in several bits of the shift register.

 In the first case, at the output of the element NOT 17, a single signal is formed: by which the issuance trigger 22 is set to the state O, the next application is received in the first storage register 37, the applications in the registers 37 are moved, and the application from the last register is transferred 37 by storage in the manner described is transferred to shift register 40.

In the second case, at the output of the element OR 24, a single potential is held, which opened the elements 15 and 16 at the second inputs. Since the shift control trigger is in the O state, the AND 16 element is closed, therefore the pulses from the output of the AND 4 element pass through the AND 15 and SHSh 24 elements to the register shift control input 41. 40 shift. According to this impulse, the contents of register 40 are shifted towards the higher bits. If there is no coincidence of the single signals on the AND 47 elements, then the next clock signals further shift the information in register 40. In this case, the shift is performed until the contents of the shift register becomes zero. Such a situation can occur either at the end of one cycle, if the number of free processors is enough to solve the problem, or for several cycles during which the state of the processors is tracked in the readiness register 61.

The service mode will continue in the order of arrival.

until the mode trigger is set to state.

 To put the device into service mode, according to a circular cyclic algorithm, it is brought to its initial state, and then, from a signal from input 10, the mode trigger 9 is set to state O.

In this mode, queuing and monitoring the state of the processors until the first application to the shift register 40 and the buffer register 53 is transmitted is similar to that considered. The difference of this mode is that before the next signal of the generator of 3 pulses, the device analyzes the possibility of distributing the free processors of the accepted application. In this case, since the zero signal is generated at the output of the element NOT 17 and the mode trigger 9 is in the state O, the AND 60 elements are closed with the zero output of the element OR 59, which fixes the number of processors free in the register 61 at the time of comparison. To compare the number of required processors with the number of free ones, the comparison circuit 13 is used, the first inputs of which are fed a binary code of the number of required processors, and the second - the binary code of the number of free processors. If the code of the number at the first input is greater than or equal to the code of the number at the second, then the value of the output signal of the comparison circuit is zero. If on the contrary, the value of the output signal is 1.

Since the number of needed and free processors is represented by the position code, in order to compare them in the comparison circuit it is necessary to convert the position codes to binary ones.

The conversion of the positional code of the number of required processors of the register 40 is performed as follows. Since the code of the number of required processors in the shift register is indicated by a single state of adjacent bits, starting with the youngest, then. The high-end number uniquely reflects the number of processors required. Hence, the task of forming the binary code 43 of the positional code is reduced to the selection of the most significant bit, i.e. converting a positional code into a unitary code (having a unit in only one position of the code), and then unitary code into a binary one.

The binary forward code from the outputs of the priority encoder 19 is fed to

the second inputs of the comparison circuit 13.

Let the number of processors need more free. In this case, the output signal of the comparison circuit is equal to one. This signal closes on the inverse input element AND 6 and opens the element AND 5 on the third input. After some time, determined by delay element 8, through element 5, it is set to state 1 trigger of record 14 and to state O, input shift register 40. The value of delay time by element 8 is determined by the transient time. in the encoder 18 and the scheme.

13 comparisons.

A single signal from the output of the element NOT 17 opens the elements AND 26 and 28. Since the trigger 14 is set to state 1, the signal

records are formed by the element And 28. For this signal, which arrives at the first control input 31 of the switch, copy the application from the buffer register 53 from outputs 54 and 55 to

the switch inputs 34 are recorded in the first register 37 of the storage group from the outputs 35 and 36 of the switch 30. After some time, determined by the delay element 7, the trigger 14

records are set to state O. The parameters of the delay element 7 are chosen based on the duration, transients in the transmission of information from the register 53 through the switch 30 and into the first register 37 of the storage group. Clock signals from the outputs of the elements And 26 moving the order in the registers 37 is similar to that considered.

In the second case, when the number of processors required is greater than or equal to the number of free ones, the output signal is less than the comparison circuit 13 is equal to zero. In this case, the And 5 element is closed at the third input, and the And 6 element opens at the inverse input. Since the trigger 9 is set to the state O, a single signal is held at the output of the element OR 23, then the pulses from the output of the delay element 8 set the shift control trigger 12 to the state 1. With this the shift pulses are fed

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from to the input 41 of the lazer by shifting the register 40 by shifting: elements AND 1 and OR 24. At the same time, a single signal from the output of element And 6 is set to the state 1) the element IL1-1 25 trigger 22 issuance ,,, In the future, the device is similar considered;

Upon completion of servicing all applications that are in the queue in the group's registers 37, as well as the application in shift register 40, the potential drop in the group of elements OR 56 and the element 17 NOT through element 57 initiates the one-oscillator 62. the one-shot 62 trigger 1 is set to the state O. I

Further, the operation of the device

starts upon arrival of a switch to switch input 33, accompanied by a trigger signal at input 2.

Claims (1)

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