SU1196866A1 - Device for distributing jobs to processors - Google Patents

Abstract

1. A DEVICE FOR JOB DISTRIBUTION TO PROCESSORS containing a control block, a shift register, a processor readiness register, a duplication register, a group of I blocks, a group of elements. OR, and an OR element, and the control block contains a trigger, a pulse generator, three And elements, and two registers , the outputs of the shift register are connected to the inputs of the OR element and to the first inputs of the blocks of elements AND groups, the outputs of the elements OR groups are connected to the single inputs of the corresponding readable bits of the processor readiness register, one The outputs of which are connected to the second inputs of the blocks of the I group elements, the outputs of the blocks of the AND elements of the group are a group of information outputs of the device, the group of signal inputs of the device is connected to the information inputs of the corresponding bits of the duplication register, so that that, in order to increase the reliability of the operation by reducing the likelihood of a denial of service for the service, it contains a storage unit for the application, a selection unit, a group of register units, a group of decoder units, the unit is occupied processors, the priority unit, PE. masking mask, encoder and one-shot group, whose codes are connected to the zero inputs of the corresponding masking register bits, the output register group of the black-out register is connected to the first group of inputs of the priority block, the outputs of the cosmic one are connected to the single inputs of the corresponding register bits (L masking and with the corresponding inputs of the digitor, the group of outputs of the encoder is connected to the first group of inputs of each block of registers of the group, the group of outputs of each block of registers of the group is connected to g Packing the inputs of the corresponding unit with the group decoders, the same outputs of each block of the group decoders are connected respectively to the inputs of the same elements of the group O) group, the unit outputs of the duplication register Od are connected to the second group of inputs of the priority block, the unit outputs of the processor readiness register are connected to the inputs of the corresponding single-vibrators the group, the group of information inputs of the device is connected to the group of inputs of the storage unit of the order, the group of information outputs of which is connected Nena with groups of input blocks and elements of group blocks the outputs of AND gates are connected to suitable groups

Description

. By the input processor unit input groups, the first output group of which is connected to the second input group groups of group registers, the first output registers of the group registers are a group of signal outputs of the device, the second group of processor output units are connected to the third groups of inputs of group registers, the outputs of which are connected to the control inputs of the corresponding blocks of the group decoders and with the group of inputs of the selector block, each output of the group of outputs of the selector block is connected to the write enable input one the name block of the group registers, and the control block further comprises a multiplexer and a memory block, the group of multiplexer inputs connected to the first group of outputs of the first register, the second group of bypasses of which is connected to the group of inputs of the second register and the output of the multiplexer, the first, second The third, fourth and fifth control inputs of which are connected respectively to the output of the storage unit of the application, to the first step of the selector, to the second output of the selector, to the output of the OR element and to the corresponding output to The second group of outputs of the first register, the group of outputs of the second register is connected to the group of address inputs of the memory unit, the group of outputs of which is connected to the group of inputs of the first register, the first, second, third, fourth and fifth outputs of which are connected respectively to the first input of the first element I, with the information input of the shift register with the first input of the second element And, with the input of the resolution of the recording of the shift register and with the first input of the third element And, the output of which is connected to the first input of the selector unit, the first output of the gene Pulse rampter is connected to the second inputs of the first, second and third elements, And the output of the second element And is connected to the shift register shift offset, the second output of the pulse generator is connected to the clock input of the first register and the clock input of the masking register, the third output of the pulse generator is connected to the clock the input of the second register and the clock input of the register of duplication, the device start input is connected to a single input and the inverse reset input of the trigger, the output of which is connected to the generator start input and pulses, the output of the first element I is connected to the clock input of the storage unit of the stack, the output of the processor's occupied block is connected to the second input of the selection block and to the reset inputs of the storage block of the blank and the shift register, the stroke of which is connected to the first input of the block of the same name elements of the group, and the output of the high bit of the shift register is connected to the information input of the lower bit of the shift register, each output of the processor readiness register is connected to the second input of the same name block of elements of the group, a third group of output rows zanyti processor unit coupled to the reset inputs PE group Giustra ready processors kazhdsh input group code input device coupled to the reset input of the block of the same name registrov..gruppy. 2. The device according to claim 1, so that the selection block contains a state register, shift register, record register, group of elements, AND, W-HCH element and Hffli element, with the group of block inputs connected to the group of unit inputs of the state register, the unit outputs of which are connected to the first inputs of the corresponding AND elements of the group and to the inputs of the element OR NOT, the first input of the block is connected to the shift input of the shift register, the group of single outputs of which is connected to the second inputs of the corresponding elements. In addition, the unit high-order output of the shift register is connected to the single input of the first bit of this register, the second input of the block is connected to the reset input of the record register, the output of the OR-NOT element is the first output of the block, the unit outputs of the register the records form a group of outputs of the block and are connected to the corresponding zero inputs of the status register and the inputs of the OR element, the output of the OR element is the second output of the block, the outputs of the AND elements of the group are connected with the single inputs of the recording register. 3. A device according to claim 1, characterized in that the processor occupancy unit comprises a counter, a decoder. A coder. A group of OR elements, an OR element, a first and a second one-shot, and the groups of inputs of the block are connected to the inputs of the corresponding. the elements of the OR group, the outputs of which are connected to the corresponding inputs of the encoder, with the inputs of the element OR, and are the third group of outputs of the block, the outputs of the encoder are the first group of outputs of the block, the output

the OR element is connected to the input of the first one-shot, the output of which is connected to the summing input of the counter, the outputs of the counter are connected to the inputs of the decoder, the outputs of which are the first group of the block, in addition, the last output of the decoder is connected to the input of the second single-shot, the output of which is connected to the reset input of the counter and with the release of the block.

The invention relates to computing and can be used as a device for distributing tasks (tasks) in a multiprocessor computing system.

The purpose of the invention is to increase the reliability of operation by reducing the likelihood of denial of service in applications.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the control unit; in fig. 3 - block diagram of the selection block; in fig. 4 shows a block diagram of a processor occupancy block; in fig. 5 is a block diagram of a device operation algorithm; in fig. 6 is a table of the operation of the priority block.

The device (Fig. 1) contains groups of information outputs 1 of the device, control block 2, request storing block 3, selection block 4, register block block 5, group of decoder blocks 6, processor occupied block 7, priority block 8, register 9 shift, processor availability register 10, duplication register 11, masking register 12, encoder 13, element OR 14, group of elements OR 15, group of blocks of elements AND 16, group one-vibrator OBS 17, group of information inputs 18 of the device, input 19 of device startup, group 20 device code inputs, group 21 signal outputs of the device output 22 of block 2, output 23 of block 3, outputs 24-26 of block 2, input 27 of block 2, outputs 28.1 and 28.2 of block 2, output 29 and 30 of block 4, group of outputs 31 of block 4, output 32 of block 2 , a group of outputs 33 of block 5, a group of outputs 34 of an encoder 13, a group of outputs 35 and 36 of block 7, an output 37 of block 7, a group of signal inputs 38 of the device, a group of inputs 39 of block 7.

Control unit 2 contains (FIG. 2) memory block 40, registers 41 and 42, trigger 43, multiplexer 44, elements I, pulse generator 48, outputs 49-51 of generator 48, outputs 52-54 of register 42, output groups 55 and 56 register 42, output 57 of memory block 40. Selection block 4 contains (FIG. 3) an element of the ISP-NE 58, a state register 59, a shift register 60, a record register 61, a group of elements AND 62, an element OR 63.

UNIT 7 occupied processors (Fig. 4) contains a decoder 64, an encoder 65, a group of elements OR 66, an element OR 67, one-shot 68 and 69, a counter 70.

Consider the operation of the device.

In the initial position, all memory elements are in the zero state of scientific research institutes except the register 10, which is in the single state. This state of register 10 corresponds to the state of readiness of processors to perform tasks.

Each task scheduled for execution by an external operating system is identified by a task number code received at the inputs 18 of the device in the form of a service application.

; . 31

llo to the start signal, arriving at input 19, the device is put into a working state. At the same time, it is advisable to consider the operation of the device in the following main modes (Fig. 5): formation of a queuing line in the application storage unit 3; search for free block g 5.1 (16) task management; assigning free processors of block 1 to perform the task; saving information about the processors performing the task; release of processors on task execution completion.

The queuing queue in block 3 is performed as follows.

By the start signal, the trigger 43 is set to the single state j and the single potential from the single output of the flip-flop 43 allows the generation of a clock grid of pulses by the generator 48. Since there is no wake in block 3, unit 23 is set to output 23. By entering the input of multiplexer 44 of block 2, this potential determines the lower-order modification of the address of the first microcommand which is written to the register 41 by the clock pulse from the output 51 of the generator 48. The microcommand selected from block 40 from the clock 48 from the output of the generator 48 is written to the register 42. The output 52 of the register 42 in this micro-command is set to one State. The pulses from the output 49 of the generator 48 through the open element I 45 are fed to the output 22 of block 2 and further to the clock input of block 3.

The application received at the inputs 18 of the device is recorded in block 3. For each clock pulse at the input 22, a synchronous shift of the block 3 and the next application from the input 18 of the device is recorded. The queuing of the queuing queue is completed after writing the entry to the last cell of block 3. At the same time, at the level 23 of block 3, the no potential is set, which completes the formation of pulses at the output of 22. block 2, since in this case the micro-command is read from block 40 d 52 which is set to zero.

The resumption of the formation of clock pulses at the output 22 of block 2 occurs after completion of the expansion of 968664

assignments, which is indicated by a single signal at the output 37 of block 7, arriving at the zero input of the reset of block 3.

J The mode for finding and assigning processors for executing a task is implemented in two stages: searching for a free block 5, which stores the numbers of the processors assigned to complete the task; search and assignment of free processors for task execution.

The functions of the first stage are performed by block 4. The initial states of the gyres 59-61 of this block to the beginning of the operation of the device are: a single state of the register 59 (this indicates that all blocks 5 are free); the single state of the first2Q th register bit .60; a single state of the first register bit 61.

Such a state of register 61 is established after the initial setup of registers 59 and 60 is completed. In this case, a single signal of setting the first bit of register 61 is formed at the output of AND 62.1, a single signal from the first bit of register 61 enters output 29 of block 4

30 through item ШШ 63, as well as set. The first bit of the register 59 is zero. Since the output potential of unit 29 is set to a single potential, the formation of clock pulses at output 32 of unit 2 is prohibited and the contents of register 60 are not shifted. This state of ime block 4 corresponds to the completion of the search phase of the free block 5. After

40 assignment of processors to task register 61 is set to zero with a signal from output 37 of block 7.. At the same time, the zero-potential is outputted at the output 29 of the block 4, and the block 2 at the output 32 produces pulses that shift the contents of the register 60 until a free block 5 is found.

After finding a free block

50 5 at the corresponding output 31 of block 4 is set to one) 1st-. the potential allowing the writing of block 5 at the stage of assigning processors.

In order to increase the reliability of the operation of the device, each task is performed on three processors, and the data obtained after its execution is used on OS5.

new majority voting on the principle of two of the three software external operating system.

Search and assignment of free processors to a task occurs in the following way.

Upon completion of the process of forming the queue of the request and searching for a free block 5, block 2 generates the recording resolution signals at pin 26 and initial setting at output 24. In this case, the unit 9 is written to the first discharge register for the first bit. By the single readiness signal from the output of the first bit register 10 opens block 16.1 of the elements AND, and the corresponding process obtains the code of the task number. At the same time, the code enters the inputs of the OR element 66.1 of block 7, at the output of which a single signal is generated. This signal is used to form the code occupied by the processor, to reset the ready signal of the occupied processor, and also to control the writing in the registers of block 5 of the code of the occupied processor.

The code of the occupied processor is generated by the encoder 65 and is fed to the output 36 of block 7. In addition, a single signal from the output of the element OR 66.1 is summed in the counter 70, arriving at its counting input through the element OR 67 and the one-shot 68.

The output code of counter 70 is fed to a decoder 64, the first output of which forms a single signal arriving at the output 35 of block 7. The decoder 64 is used to determine whether the task has completed distribution.

At the start of operation of the device for storing the codes of the processors assigned to solve the problem, block 5.1 is selected (Fig. 1).

The code occupied by the processor from the output 36 of block 7 is fed to the first inputs of block 5.1.

When the first processor is assigned, a single signal is set at the output of AND 62.1, and the code of the occupied processor is written to register 5.1.

On the next clock pulse arriving at the input of the shift re968666

the horn 9 is from the output 25 of block 2; a circular cyclic shift of the contents of this register is carried out. For this example, a single signal is set at the second output of register 9. At the same time, the task code is set at the output of the 16.2 element I. In the future, the process of occupying the corresponding

The processor proceeds as described above, namely, in the counter 70 of block 7 (FIG. 7), the value is increased by one, which corresponds to the choice of the next register in the block

5 5.1 for recording and storing the code of the second processor assigned to the task. In addition, the ready signal of the corresponding processor in register 10 is reset by a single

0 by a signal from the output of the element OR 66.2 of block 7, coming from the group of outputs of block 7 to the corresponding zero input of the register 10.

After assigning a third processor to solve a problem, the search mode and assignment of free processors to the task is completed. In this case, a single potential is established at the third output of the decoder 64,

30 which is used to write into the third register of block 5.1 of the code of the third processor assigned to the task and reset the counter 70 of block 7 to the negative front of a pulse generated by the one-shot 69. The pulse from the output of the one-shot 69 goes to output 37 of the block 7, in which the register is set to the zero state 9, block 3 (fig. 3)

40 and register 61 of block 4.

After the block 3 is set to the zero state, a single potential is established at the output 23, by which the formation of pulses at the output 25 of the block 2 is prohibited and the formation of pulses at the output 22 of this block is allowed. In the future, the operation of the device according to the purpose of the processors proceeds similarly

50 reviewed. The queuing modes of the quotation in block 3 and the search for a free block 5 are implemented similarly to that considered.

The search mode and the assignment of free 55 - th processors are implemented upon completion of the first two modes.

Consider the implementation of the processor release mode upon completion of 7 tasks. This mode is implemented in parallel with the operation of the device in the modes discussed above. Upon completion of the task, the processor exposes a single potential of the ready signal at one of the inputs 38. A clock pulse from the output 28.1 of the block 2, after the control input of the register 11, controls the readiness signals to the register 11. From the outputs of the register 11 the signals availability goes to priority block 8, which from among all incoming processor readiness signals a signal of the highest priority processor. The priority of the processor is determined by the fact that it is connected to the block-8, the operation of which is explained in the table (Fig. 6). The output signal of block 6 is fed to the inputs of the encoder 13, which forms the code of the processor to be released. This code is fed to the inputs of blocks 5 and is compared with the codes recorded in this block. In the case of alternate coincidence of all the codes recorded in block 5, with the codes arriving at input 34, a single signal is set at the output 21 of this block, which is fed to a group of outputs 21 of the device. After that, the pulse from output 28.2, arriving at the control input of register 12, is set to a single state of the register 12, corresponding to a single signal at the output of block 8, then the process readiness signals from the inputs 38 to the register 11 are recorded again and the release latching process is repeated. The signals to the device outputs 21 inform the upper level processor of the computing system 668 of the completion of the task. The upper level processor performs software majorization of the results of the operation of three processors and exposes a release signal to the processors at the inputs 20 of the device. From the corresponding input 20, the release enable signal is fed to the reset input of the corresponding block 5, a single signal from the output 33 of which is fed to the control input of the corresponding block 6. In block 6 corresponding to the released block 5, the codes of the processors being released are decoded, and the outputs a single signal from the upstream of block 6 through the corresponding elements OR 15 will restore the ready signals of the corresponding processors in register 10. Thereafter, the processors and block 5 that completed the task and may be assigned to perform the next job from the queue unit 3. The work device is completed upon release of the stop signal from the input device 19. In this case, the trigger 43 of block 2 is set to the zero state and prohibits the generation of the clock pulse grid by the generator 48. In the event of a change in the configuration of the processor field associated with conducting preventive or repair work, the corresponding register register 10 is not set to one. This corresponds to the state of the corresponding processor that is not assigned to perform tasks. In the future, this processor can be turned on without stopping the device.

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Claims (3)

1. DEVICE FOR DISTRIBUTING TASKS TO PROCESSORS, comprising a control unit, a shift register, a processor ready register, a duplication register, a group of blocks of AND elements, a group of elements. OR and an OR element, the control unit comprising a trigger, a pulse generator, three AND elements and two registers , the outputs of the shift register are connected to the inputs of the OR element and to the first inputs of the blocks of elements AND groups, the outputs of the elements OR groups are connected to the unit inputs of the corresponding bits of the processor readiness register, unit outputs which are connected to the second inputs of the blocks of elements of the I. group, the outputs of the blocks of elements and groups are a group of information outputs of the device, the group of signal inputs of the device is connected to the information inputs of the corresponding bits of the duplication register, which is made in order to increase - the reliability of the operation by reducing the likelihood of denial of service applications, it contains a block for storing applications, a selection block, a group of register blocks, a group of decoder blocks, a processor occupation block, b approx priority PE. masking wizard, encoder and one-shot group, the outputs of which are connected to the zero inputs of the corresponding bits of the mask register, the masking register output group is connected to the first group of inputs of the priority block, the outputs of which are connected to the unit inputs g of the corresponding bits of the masking register and with the corresponding inputs the encoder, the group of outputs of the encoder is connected to the first group of inputs of each block of the registers of the troupe, the group of outputs of each block of registers of the group is connected to the group of inputs the corresponding block of the group decoders, the outputs of each block of the group decoders are connected respectively to the inputs of the same elements OR groups, the individual outputs of the duplication register are connected to the second group of inputs of the priority block, the individual outputs of the processor readiness register are connected to the inputs of the corresponding single-vibrators of the group, the group of information inputs of the device is connected to a group of inputs of a block for storing applications, a group of information outputs of which is connected to groups of inputs of blocks of ele cops And groups, outputs of blocks of elements And groups are connected to the corresponding 9989611 '· ’П5. the input groups of the processor occupation block, the first group of outputs of which is connected to the second groups of inputs of the group registers blocks, the first outputs of the group registers blocks are the group of signal outputs of the device, the second group of outputs of the processor occupation blocks is connected to the third groups of inputs of the group registers blocks, the outputs of which are connected to the control inputs of the respective units of the decoders of the group and with the group of inputs of the selection block, each output of the group of outputs of the selection block is connected to the recording permission input one the name block of the group registers, and the control unit further comprises a multiplexer and a memory block, the group of inputs of the multiplexer connected to the first group of outputs of the first register, the second group of outputs of which are connected to the group of inputs of the second register and the output of the multiplexer, first, second, third, the fourth and fifth control inputs of which are connected respectively with the output of the application storage unit, with the first output of the selection unit, with the second output of the selection unit, with the output of the OR element and with the corresponding output of the second groups of outputs of the first register, the group of outputs of the second register is connected to the group of address inputs of the memory block, the group of outputs of which is connected to the group of inputs of the first register, the first, second, third, fourth and fifth outputs of which are connected respectively to the first input of the first element And, with the information input the shift register, with the first input of the second AND element, with the write enable input of the shift register and with the first input of the third AND element, the output of which is connected to the first input of the selection block, the first output of the generator is imp LSS is connected to the second inputs of the first, second and third elements AND, the output of the second element And is connected to the shift register shift input, the second output of the pulse generator is connected to the clock input of the first register and to the clock input of the mask register, the third output of the pulse generator is connected to the clock input of the second register and with the clock input of the duplication register, the device start input is connected to a single input and to the inverse trigger reset input, the output of which is connected to the pulse generator start input, the output the first element Й is connected to the clock input of the application storage unit, the output of the processor occupation unit is connected to the second input of the selection unit and to the reset inputs of the application storage unit and the shift register, each output of which is connected to the first input of the same unit of elements of the group AND, and the output of the oldest the shift register bit is connected to the information input of the least significant shift register bit, each output of the processor readiness register is connected to the second input of the same block of elements AND groups, the third group of outputs of the occupancy block rotsessorov connected to the reset inputs PE group Giustra ready processors, each input group code input device coupled to the reset input of the homonymous block registrov.gruppy. 2. The device according to claim D, with the proviso that the selection block contains a status register, a shift register, a write register, a group of elements. AND, an OR-HE element and an OR element, and the group the unit’s inputs are connected to the group of single inputs of the status register, the unit outputs of which are connected to the first inputs of the corresponding elements of the AND group and to the inputs of the OR-NOT element, the first input of the unit is connected to the shift input of the shift register, the group of unit outputs of which is connected to the second inputs of the corresponding elements and groups, in addition, e the digital output of the upper bit of the shift register is connected to the single input of the first bit of this register, the second input of the block is connected to the reset input of the write register, the output of the OR-HE element is the first output of the block, the single outputs of the write register form a group of outputs of the block and are connected to the corresponding zero inputs of the register the state and inputs of the OR element, the output of the OR element is the second output of the block, the outputs of the elements AND groups are connected; with the unit inputs of the write register. 3. The device pop. 1, characterized in that the processor occupation block comprises a counter, a descrambler, an encryptor, a group of OR elements, an OR element, the first and second one-shot, and the groups of inputs of the block are connected to the inputs of the corresponding ones. OR elements of the group whose outputs are connected to the corresponding inputs of the encoder, with the inputs of the OR element and are the third group of outputs of the block, the outputs of the encoder are the first group of outputs of the block, the output of the OR element is connected to the input of the first one-shot, the output of which is connected to the summing input of the counter, the outputs of the counter connected to the inputs of the decoder, the outputs of which are the first group of the unit, in addition, the last output of the decoder is connected to the input of the second one-shot, the output of which is connected to the reset input with etchika and output unit.