SU1069000A1 - Storage - Google Patents

Abstract

A STORAGE DEVICE containing memory blocks, a switch, a control unit and a register whose information inputs are in-. the formation inputs of the device, the control input of the register are the first control input of the device, the first and second outputs of the register are connected respectively to the first and second inputs of the curing unit, the third and fourth inputs of which are the second and third inputs of the device, respectively, the first and second outputs The control units are, respectively, the first and second outputs of the device, the outputs of the switch are information outputs of the device, different. All that in order to increase the speed and reliability of the device, it contains synchronization blocks, blocks of information registers, a block of buffer registers and a block of address registers, the output of which is connected to the fifth input of the control block and to the control input of the switch, the first input of the block of registers addresses are connected to the first input of the control unit, the third and fourth outputs of which are under-. the keys to the second and third inputs of the address register block, respectively, the information inputs of the commutator, are connected to the information outputs of the memory blocks, whose information inputs are connected to the information outputs of the corresponding blocks of the buffer registers, the address inputs of the memory blocks are connected to the address outputs of the corresponding blocks; coves of the buffer registers, the first control outputs of which are connected to the first inputs of the corresponding synchronization blocks, the second control outputs of the blocks of the buffer registers (pod-); The keys are connected to the second inputs of the corresponding synchronization blocks, the first outputs (whose outputs are connected to the first control inputs of the corresponding blocks of the buffer registers, the second I control outputs of the synchronization are connected to the control inputs of the corresponding memory blocks, the third outputs of the synchronization blocks are connected to the first control the inputs of the corresponding blocks of registers of inl formation, the second control inputs of which are connected to the fifth output of the control unit, the first control outputs of the blocks of registers of information They are connected to the sixth input of the control unit, the seventh input and the sixth output of which are connected respectively to the third control output and BTojx and control inputs of the buffer register blocks, the second control outputs of the buffer register blocks are connected to the third inputs of the corresponding synchronization blocks.

Description

The invention relates to computing and can be used to build memory blocks with improved performance.

It is known to store a device containing memory blocks, a communication block controlling the receptions with information output, a priority block and a buffer memory in which one or several buffer registers correspond to each memory block. In this device, the procedure for issuing information is performed by a priority block. Moreover, when issuing information, the following rule is observed: aa issue issuance is processed by the communication unit only under the condition of issuing information on all previous calls.

Priority handling of research institutes is most often carried out with the help of a contact count and a priority sign count. With each call, a unit is added to the call counter, and a counter reading, which is based on priority signs and stored in a buffer, is assigned to the address, and if information is issued, a unit is added to the priority sign counter, thereby preparing information for the next order the treatment, the priority attribute of which coincides with the current value of the counter of the priority attribute D the disadvantage of the device is the complexity caused by the necessity of spending a large amount of equipment vanii and communications for the organization of management.

The closest technical solution to the invention is a memory device containing memory blocks, a control unit, a buffer register of the address, a switch, the first and second inputs of the control unit. connected to the corresponding outputs of the buffer register of access, the third and fourth inputs,: the first and second outputs. to the corresponding inputs and outputs of the device. The control of information output in this device is carried out with the help of inversion counters and priority sign 2.

The disadvantages of the known devices are the complexity, limited reliability and speed. The devices have a significant amount of equipment (call counters and priority signs, priority signs registers and comparison circuits in each memory block), a large number of control links and, as a result, complex control automata. The absence of a queue of calls to the memory blocks and the need to wait for the release of their output registers

numbers from previous information reduce the effective speed of this device.

The purpose of the invention is to increase the speed and reliability of the device.

This goal is achieved by the storage device containing memory blocks, a switch, a control unit and a register whose information inputs are. are the information inputs of the device; the control input of the register is the first controlling input of the device; the first and second outputs of the register are connected to the first and second inputs of the control unit, the third and fourth inputs of which are respectively the second and third inputs of the device, and the first and second the outputs of the control unit are respectively the first and second outputs of the device, the outputs of the switch are information outputs of the device, includes synchronization blocks, blocks of information registers , block-buffer registers and a block of address registers, the output of which is connected to the fifth input of the control unit, and to the control input of the switch, the first input of the block of address registers is connected to the first input of the control, the third and fourth outputs of which connected, respectively, to the second and third inputs of the block of address registers; information inputs of the switch, connected to the information outputs of the PY1MYA.TI, and IN - blocks.

the focus inputs of which are connected to the information outputs of the corresponding blocks of the buffer registers, the address inputs of the memory blocks are connected to the address outputs of the corresponding blocks of the buffer registers, the first control output of which are connected to the first inputs of the corresponding synchronization blocks, the second control outputs of the blocks of the buffer registers are connected to the second the inputs of the corresponding synchronization blocks, the first outputs of which are connected to the first control inputs of the corresponding blocks of the buffer register c, the second control outputs of the sync blocks are connected to the control blocks. the inputs of the corresponding memory blocks, the third outputs of the synchronization blocks are connected to the first control inputs of the corresponding blocks of the information registers, the second control inputs of which are connected to the fifth output of the control block, the first control outputs of the information register blocks are connected to the sixth input of the block control, the seventh input and the sixth output of which are connected respectively to the third control outputs and the second control inputs

the buffer register blocks, the second, control outputs of the buffer register blocks are connected to the third inputs of the corresponding synchronization blocks

FIG. 1 shows a block diagram of a memory device; in fig. 2, the synchronization blocks in FIG. 3 control unit; in fig. 4 block bu, fern registers (similar construction have blocks of information registers and blocks of address registers). .

The storage device contains a buffer register 1, blocks of buffer registers, where rf is the number of memory blocks, blocks, memory, block of information registers, blocks 5;, Sf, synchronization {; and, switch 6, block 7 of control, block 8 of address registers . The buffer address register has information inputs 9 (address code), 9 (recording information krda. |; 9z (operation code J, information outputs 10, pack {input 11 input - record input. Each of the 2 buffer register blocks has information: inputs 12, control input 13 input information recording, control

.; vchsod 14 -. information shift input, information outputs 15 (15. - sign of operation code, 15g - code of recorded information, 15h address code), control output 16 - sign output of no information in the buffer registers, control output 17 - sign of the absence of free buffer registers.

Each of the 3 memory blocks has

.address inputs 18, informational

19, control inputs 20, information outputs 21. Each of the 4 buffer register blocks 4 has information inputs 22, control input 23 is an information recording input, control input 24 is an information shift input- information outputs 25, an output 26 - the output of the sign of the absence of information in the buffer registers, the control output of 27 t the output of the sign of the absence of free buffer registers. Each of the synchronization blocks 5 has: .. input 28 - an operation code input, 29 second - a signal input The reference buffer is empty, input 30 - a signal input Information buffer is full, output 31 is an output of the Shift signal, output 32 is the drive control signal outputs , output 33 - signal output Record.

Switch 6 has information inputs 34, control inputs 35, information outputs 36. Control unit 1 has input 37 (inputs of address memory block address code) input 38.- input of operation code, input 39 input of signal Reversal, input 40 of signal input Resolution information output, input 41 — memory address block code inputs, controlling the output information, input 42 — signal inputs Information buffer is empty, input 43 signal inputs, the reference buffer is full, output 44 is the signal output Reverse received, output 45 is the signal output Appeal serviced, exit 46 - exit sig ala shift in the buffer memory address blocks, yield 47 - Recording signssha output buffer addresses in the memory blocks 48 output - outputs shift signals in the data buffer 49 output - outputs recording signals in buffer references. Block 8 of the address registers has an input 50 (information inputs /, input 51 input information recording, input 52 input information shift, outputs 53 (information outputs 7. Synchronization unit 5 contains an OR 54 element, AND 55 element, control signal generator 56, which can be performed either on delay elements, or on the principle of a counter-decoder.

The control unit 7 contains AND elements, a decoder 58, an OR element 59, a delay element 60, a trigger 61, an AND element 62, an AND-OR element 63, a decoder 64, an AND element, 1 ,, the delay element 66.

The block 2 of buffer registers (Fig. 4 | contains buffer registers 67. | -67jj, a decoder 68, a delay element 69, a reversible counter 70, an AND-NE element 71, a stage OR 72.

In the proposed device, yjnpasl is provided by issuing information from the buffer registers of memory block addresses. When receiving a read with the information, the address of the corresponding evy memory block is entered into the last of the free registers of the buffer registers of the addresses of the memory blocks and as information is issued for the previous appeal of the adv to its output. Thus, at the output of the block of buffer registers of addresses of the blocks of memory, there is always the address of the FPIC block, from which information must be received at the current moment. Increasing the effective speed} of the device is achieved by a more complete load of memory blocks due to the possibility of creating a queue of calls and ahead of the read information in each of them.

The reception and processing of calls in the proposed device is carried out as follows. .

When the address arrives in the inverter, the code of the recorded number I.B in the case of a write operation / soda operation is recorded in the register I, and the inversion signal is sent to the third input 39 of the control unit 7

which sets in one state the trigger 61. A single signal from the output of the trigger 61 allows the decoder LB to work, the input of which is supplied with the address code of the access memory from the corresponding output of the register 1. The signal from the output of the decoder 58 is fed to the first input of the And 57, on the second inlet: one from the third output 17 of the block 2 of the buffer registers via sed. my vhbd 43 block 7 receives a signal The buffer is full. If block 2 of the buffer reference registers is not completely filled, this signal has a single value and permits the formation of a signal at the sixth output 49 of the block 7. Writing to the access buffer using which the information from the register is overwritten into the last of the free registers of block 2. The signal from the output of the And 57 , the passage also through the OR element 59 and the delay element 60, resets the trigger 61 to the zero state, generates a signal at the first output 44 of the block 7 Signal to accept a new access to the device, and goes to the first th input of the element And 62 If the received treatment is with reading information, the second input of the element And 62 is from the corresponding output of the register 1-. through the second input 38 of block 7, a single signal arrives and at its fourth output 47 generates a SI signal. Writing to the memory buffer of the memory block, rewriting the memory block address from the register. 1 to the outermost of the free buffer registers of block 8. Delay element 60 is needed to form the desired duration of the control signals.

Block 2 of the buffer register of references has a 70-bit counter, where rm7 is the number of buffer registers in the block. Before work counter 70 is reset. The zero code of the counter allows the selection of the first output of the decoder 68 and generates a zero signal at the output of the OR 72 element. The access buffer i is empty Signal Writing to the access buffer i on the second input 13 of block 2 allows the formation of a write signal to the buffer register 67 on the first output of the decoder 68 and The passage through the delay entry element 69 to the addition of the counter 70 increases its content by one, preparing the record in the second buffer register 67, and so on.

The entry of the call code into the corresponding buffer registers is performed by their first information inputs connected to the first information inputs 12 of block 2. The second information inputs of the buffer registers are connected to the outputs of the previous registers and form information shift circuits. After the processing by the i-th memory block is completed, the Shift signal enters the shift inputs of the buffer registers 67 and the subtraction inputs of counter 70 via the third input 14 of block 2. In this case, the information from the lower buffer register is overwritten to a higher one and the counter content decreases. 70 per unit. In the case of a full buffer, the unit code of the counter 70 forms a zero-signal at the output of the element AND-NOT 71. The reference buffer i is full. A single signal from the second output 16 of the block, indicating that there are accesses to the memory block i, is fed to the second input 29 of the synchronization block 5 and allows the control generator 56 to start. The start of the FOILER 56 is carried out by a signal from the output of the element 55, gated by the control frequency at one of the inputs of the circuit. After starting the imaging unit 56, the signal from its output blocks element I55 for the duration of the operation of the memory block. Blocking the trigger signal of the generator 56 can also be accomplished by a zero signal from the output of the element OR 54, if the i-th memory block is accessed with reading information (the zero signal of the operation code on the first block 28 and its block 4 is fully occupied (zero the information buffer signal is filled at the third input 30 of block 5; I. After performing the read operation from the outputs of the imaging unit 56, through the first output 31 of block 5, the third input 14 of block 2 / receives a Shift signal preparing the following access to the i-th memory block, and cher From the output 33 to the input 23 of block 4, a signal is a record that writes the read out information from the 3-j accumulator to the extreme of its free registers of the read information. The control signals from the outputs of the former 56 through the outputs 32 of the block 5j are fed to the inputs 20 drive 3.

The principle of operation and the block diagram of blocks 2, 4 and 8 of the buffer registers are the same, therefore, their work is described briefly in the following. Consider the operation of the device when issuing the read information. In the process of receiving and processing requests, the buffer registers of block 8 sequentially in the order of their arrival are located the addresses of memory blocks of calls with information reading, and c. the buffer registers of blocks corresponding to the information in the order of its reading from the memory blocks; the code address of the memory block from which the information should be supplied first

It is always in the upper buffer register of block 8 and from its output 53 it goes to the direct-play of the inputs 35 of the switch b, connecting its output 36 to the outputs 25 of the block 4 and to the inputs 41 of the control block 7. The address of the inputs 41 of the block 7 is fed to the inputs of its decoder 64 and selects the i-and the output of the decoder. The i-ro signal of the output of the 4 encoder is fed to the corresponding input of the element AND-OR 63 and the first input of the element AND 65. A single signal from the output 26 of block 4 arrives at the corresponding input 42 of block 7, confirms readiness for readout information and generates element AND-OR 63 signal Circulation is serviced, which is output to the system from output 45. This signal from the system to the input 40 of block 7 is emitted by a signal. Allowing the output of information, arrivals at the second input of the element And 6-5 and the element 66 of the delay. At the output of the element 65, a signal is generated which, through the corresponding output 48 of block 7, enters the input 24 of block 4 and shifts the information in it. Next, the signal from the output of the delay element 66 through the output 46 is fed to the input 52 of the block 8 of the address registers, shifted in it and thereby preparing the device to issue information on the next call.

The feasibility advantage of the proposed device is to simplify and increase reliability by using address buffering of the access memory blocks to manage the information tasks, and improving efficiency: speed by more fully loading the memory blocks achieved by separate buffering of the memory blocks and read ;: of which information.

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Claims (1)

A MEMORY DEVICE containing memory blocks, a switch, a control unit and a register, the information inputs of which are information inputs of the device, the control input of the register is the first control input of the device, the first and second outputs of the register are connected respectively to the first and second inputs of the control unit, the third and fourth the inputs of which are respectively the second and third inputs of the device, the first and second outputs of the control unit are respectively the first and second outputs of the device, the switch outputs are information outputs of the device, characterized in that, in order to increase the speed and reliability of the device, it contains synchronization blocks, information register blocks, a buffer register block and an address register block, the output of which is connected to the fifth input of the control unit and to the control input of the switch , the first input of the block of address registers is connected to the first input of the control unit, the third and fourth outputs of which are connected respectively to the second and third inputs of the block of registers hell ECU, the information inputs of the switch are connected to the information outputs of the memory blocks, the information inputs of which are connected to the information outputs of the corresponding blocks of buffer registers, the address inputs of the memory blocks are connected to the address outputs of the corresponding blocks of buffer registers, the first control output of which is connected to the first inputs of the corresponding blocks synchronization, the second control outputs of the blocks of buffer registers are connected to the second inputs of the corresponding synchronization blocks, the first outputs which are connected to the first control inputs of the corresponding blocks of buffer registers, the second control outputs of the synchronization are connected to the control inputs of the corresponding memory blocks, the third outputs of the synchronization blocks are connected to the first control inputs of the corresponding blocks of information registers, the second control inputs of which are connected to the fifth output of the control unit, the first the control outputs of the blocks of information registers are connected to the sixth input of the control unit, the seventh input and the sixth output of which is connected us respectively to the third control outputs and the second control inputs of the buffer register units, the second control outputs of the buffer register units are connected to respective third inputs sync blocks.