SU536524A1 - Memory device - Google Patents

Description

(54) STORAGE DEVICE

iKOMiMyiaTopa inputs are connected to the outputs of the code comparison unit, the fifth inputs of the switch are connected to the accumulator outputs, the second inputs of which are connected. To one of the switch outputs, the other outputs are connected to the inputs of the P1 amplifiers; the second outputs of the additional selection unit, one of the inputs of which is connected to the outputs of the numeric current recorder, the other inputs of the additional selection unit are connected to the third outputs of the selection unit, four The third output of the selection unit, the third output of the additional selection unit, is connected to the inputs of the code comparison block.

The drawing shows a functional diagram of the storage device.

The storage device includes the storage unit /, the selection unit 2, the formers, 3 readout thicknesses, which are connected by their outputs to the inputs of the selection unit 2; control unit 4, the numeric formers, and records 5; odds, worlds of bit TOiKa write (J; read number register 7j read amplifiers 8, additional selection block: to 9, switch 10, code comparison block 11, register h, write record 12, address bus 13, control bus 14, bus 15 numbers

The storage device works in the following way.

On the address 13 buses, the read address register of the selection unit 2 is entered in the 1K01D address of the first cell from which information is to be selected, and the control unit 4 receives the sync pulse start memory on the control buses 14. In the address decoder, the coordinate wires X and the coordinate wires F are decrypted separately. The address inputs of the read sampling matrix of the selection unit 2 and the address 1 read inputs of the switch 10, which determine the selected cell, will be selected. The control unit 4 excites the formers 3, which both the readout and the full readout arrive at the numerical wire, which (Selected by the read sampling matrix of the selection unit 2.

When you first access the storage device, the coordinate wires X that penetrate the storage elements of the first cell and intersect the first selected number of wires, will be connected by switch 10 to the inputs of read amplifiers 8, the read signals will excite S amplifiers and read the following number in the number register: v. 7 7 postulIT read information. On tires, the 15th number i; n | fordi is derived from the wrinkling device. In addition, the read information is also transferred to the register of the register number 12 for regeneration into the first memory cell. The address of the first one is deleted from the register of the number of readings of the selection unit 2 to the register of the number of entries of the additional selection unit 9, and simultaneously the 3 registers of the readout address of the selection unit 2, the address of the second cell is entered from address 13 buses, from which information must be selected.

Again, as in the first treatment, the control bus 14 is supplied with a synchro-pulse of the memory device and the total read current from which the memory elements are switched on the numerical wire of the second cell.

A: At the same time, the additional selection unit will select the first numeric wire and the zero | O record will be received from the excited current generators of record 5 through the selector unit 9 iB and the first numerical wire in the opposite direction compared to the first access to the memory device. The record half has not yet switched memory elements, and therefore, by means of the X or Y coordinate wires the piercing elements of the first numerical wire are also served by the half-current recording unit of the information unit. In this case, the register of record number 12 is excited only by the formers of the current record, corresponding to the discharge of accumulator 1, into which the information unit must be written (regenerated).

The code comparison unit // compares the parts of the address codes that define the coordinate wires X of the first and second cells and, if they are equivalent, switches the switch 10 to the coordinate wires Y.

The switch 10 connects the coordinate wires K, which penetrate the storage elements of the second cell, to the inputs of the read amplifiers 5, and the coordinate wires U, which penetrate the memory elements of the first cell, to the outputs of the discharge drivers, that is, the recording 6. At the same time, the information from the second cell goes through readout amplifier 8B readout number register 7, and coordinate wires Y, which penetrate the 3 alominating elements of the first cell, will receive only recordings and the information will be regenerated into the first cell. The new information is recorded in the memory cell in two cycles: in the first cycle, information is read from the given lottery information cell and the new number is written in the register number 12 in the input buses of the number 15; in the second cycle, the new il | f. in the cell and read information from the following, as described above.

Compared with the performance of storage devices software systems 2D, 2 / 2D and ZD, the proposed solution improves the speed of memory devices made

on magnetic elements, twice, and if we consider that the speed of electronic computers is usually determined by the speed of the memory, the proposed solution will lead to a significant increase in the speed of the computer as a whole.

Claims (2)

1. Katzan G. “Computational masses of the system 370, M,“ Mir, 1974, p. 23. 2. Krayzer L.P. "Device for storing discrete information. L., “Energie, 1969, p. 123. 3 13