SU515158A1 - Random access memory with access to a plurality of memory cells - Google Patents

Description

one

This invention relates to memory devices.

A random access memory device with simultaneous access to a plurality of memory cells is known, containing a drive whose inputs are connected to a recording-regeneration unit and an address unit, and an output to a read amplifier unit, number registers whose inputs are connected through elements I to the output of the force unit - read cells, mask registers, the outputs of which are connected to the inputs of the mask generation units.

A disadvantage of the known device is the low speed of operation.

To increase speed, the device contains OR elements, additional AND elements, additional mask register and number registers whose inputs are connected respectively to the outputs of some AND And additional outputs of one of the mask generation blocks, and outputs through serially connected other additional AND elements and ORIC elements the inputs of the recording-regeneration unit.

The drawing shows a block diagram of the proposed device.

The device contains a drive 1, a block of read amplifiers 2, f of elements AND 3 (G is the bit depth of memory cells of accumulator 1), registers of numbers 4, elements of AND 5, number of issue b, write-regeneration block 7, address block 8, providing the choice section of the accumulator, which is accessed, control unit 9, additional mask register 10, 2 L additional elements AND 11 and 12, additional registers of numbers 13, f additional elements AND 14, G elements OR 15, block 16 forming a mask in recording mode containing elements AND 17 block 18 is formed and masks in read mode, containing AND 19 elements, a block of registers 20 containing mask registers 21 and 22, respectively, on X and Y coordinates for write mode and mask registers 23 and 24, respectively, on X and Y coordinates for read mode.

Claims (1)

In addition, the device contains an installation bus 25, which provides the output of the device setting signal Q to the zero initial state, the address bus 26 for issuing the address reception signal O, the read bus 27, providing the generation of a signal for starting coordinate currents Q, the bus station 28 to issue a tuning signal Q, a inhibit bus 29, providing a signal Q to start the inhibition currents, transmitting bus 30 to issue a signal Q allowing the transfer of a set of 1 numbers read from the accumulator to arif A metric device (not shown in the drawing), a bus of the number 31, which provides Bbiaa4v of the signal Q that allows multiple numbers from the arithmetic unit to the additional registers of device numbers, f buses of reception 32 numbers of arith | 1 device. Register 10 consists of flip-flops 33. Mask 10 register registers and additional number-13 registers are connected respectively to the outputs of additional elements M 12 to the outputs of the mask-forming unit 16 in recording mode, and the outputs through serial connected additional elements 11-11 and elements IL1-1 15 - to the inputs of the recording-regeneration unit 7 The device operates as follows When the signal from the control unit of the digital computer to the control unit 9 is addressed. The following sequence of operation of the device units is provided. The Q signal (Shtina 25) is used to extinguish the preceding information in registers 4, 10, 13, 21-24 and in the address registers of the address block 8. On the Q signal (bus 26), the address registers are located along the X and Y coordinates of the address block 8 receiving addresses A and A of the section; registers 21, 22 — receiving mask codes by X and Y coordinates in write mode; into registers 23, 24 — receiving mask codes by X and Y coordinates in read mode. When the signal Q appears on the bus 27 of the control unit 9 by the address block 8, the contents of all cells of the corresponding section of the accumulator 1 are read. By this time, it is formed by the write and read mask units 16 and 18, respectively. Mask resolution in the recording mode is formed by block 16 so that the / -th trigger 33 of the mask register 10 is entered into one, if the /th cell of the selected cross-section is to record the number arriving via the input buses 32 into the register 13 33 of the register 10 remains in the zero state if the information from the I register of the number 4 is to be recorded in the i-th cell of the selected section, i.e., the information read earlier is to be regenerated. Mask bits in the recording mode are recorded in the corresponding trigger 33 of the mask register 10. Triggers 33 of the register 10, containing single masks of the mask, prepare for operation the corresponding elements AND 14. Triggers 33 of the register 10, containing zero mask masks, prepare for operation the corresponding elements 11, Simultaneously with reading information from accumulator 1 by signal Q, taken from strip 31, it is decided to receive into additional registers 13 a set of numbers to be written to the accumulator. Simultaneously with reading the information from the accumulator 1 and its reception in the corresponding registers of numbers 4, the set of numbers to be written into the additional registers 13 is received. When appearing on output strip 29, the signal Q entering the recording-regeneration unit 7, as well as to each element 11 and 14, is carried out in the usual way recording into the corresponding cells of a selected section of a set of numbers received from the arithmetic device to be written to the drive 1 and nah: in the corresponding additional registers of the numbers 13 on the one hand, and the regeneration of the contents of those cells of the selected section, the contents of which were read into the corresponding registers of the numbers 4. Issue of the read The opiate 1 numbers are produced through the AND elements 5 by the control signal Q, which is generated on the output OS bar simultaneously with the signal Q. The preparation for the operation of the corresponding elements AND 5 is carried out using the output signals of the mask generation unit 18 in the read mode. Claims of the invention A random access memory with access to a plurality of memory cells comprising a drive whose inputs connected to the record-regeneration unit and the address block, and the output to the read amplifier section, number registers, which are connected through the elements AND to the outputs of the read amplifier section, mask registers, whose outputs are connected to the inputs of the mask generation blocks, differently that, in order to increase speed, it contains OR elements, additional AND elements, additional mask register and number registers, whose inputs are connected respectively to the outputs of some additional AND elements and to the outputs of one of the shackles forming masks, and exits through the series connected elements and other additional elements and -Or - to the inputs of the recording unit-regeneration.