SU743031A1 - Memory - Google Patents

Description

This invention relates to automation and computing. Memory devices are known that contain a drive, sensors of the address code, address decoders, groups of AND and OR elements that connect the address code sensor to the address decoder, input and output information buses to the corresponding buses of the device l. The drawback of the device is that for the case of recording a multi-bit code, it is necessary to add additional equipment to the bit part of the memory (matching devices, additional bits of the drive) or to reduce the frequency of access to the memory device, which is associated with the additional time spent on the formation of the address code. for writing (reading) redundant bits, an information code. The closest in technical terms is a memory device which contains a drive, an address decoder, an address code sensor with outputs connected directly to the switch and an address code sensor with outputs connected to the switch via inverters (address code sensor with direct and HHBepciibiMH outputs) switchboard (first and second groups of elements AND), signal extraction circuits (third and fourth groups of elements AND), OR elements, frequency dividers, control symbols f2j. The disadvantage of this device is the limited possibilities for recording an information code with the number of rounds exceeding the number of bits of the accumulator. The purpose of the invention is to expand the field of application of the device under the condition of minimal time and hardware costs by recording the information code with the number of bits exceeding the number of bits of the drive.

The supply chain is achieved by the fact that in memory a device containing a drive, one of the inputs of which is connected to the outputs of the elements, the other inputs of the storage device are connected to the outputs of the address decoder, the inputs of which are connected to the outputs of the first and second elements I, the first inputs of which are connected to the outputs sensor address code, the accumulator outputs are connected to the first inputs of the third and fourth And elements, the second inputs of the third And elements are connected to the interrogation bus and to the second inputs of the first And elements, the third inputs of the third And elements and the second inputs of the fourth elements And are connected to the cable resolution, the outputs of the third and fourth elements And are connected to the outputs of the device, the write resolution bus and the in-. tire tires, the entry element has been added, the fifth and sixth elements AND,

the outputs of which are connected to the inputs of the OR elements, the first inputs of the fifth and sixth elements I are connected to the information buses, the second inputs are connected to the recording resolution bus, the third inputs of the fifth elements I are connected to the interrogation bus and the input of the delay element that you have connected the second inputs of the second elements And, the third inputs of the fourth and sixth elements I.

The essence of the invention is illustrated in drawing.

The device contains an accumulator 1, an address decoder 2, an address code sensor 3 having direct outputs 4 and inverse outputs 5, first, second,

third, fourth, fifth and sixth elements 6-11 AND, delay element 12, elements 13 OR, polling bus 14, information buses 15, write resolution bus 16, bus 17 read resolution and device outputs 18

The device works as follows.

The signal change the address to the input of the sensor 3, the address code,. at its outputs, 4 g 5, direct and inverse address codes are generated, respectively. When the signal is polled to the bus 14, the accumulator is polled first at the address corresponding to the direct address code, and then the same interrogation pulse delayed by delay element 12 j provides polling the accumulator using the inverse code a / jpeca. A google recording (bus 16 is supplied with a signal permitting recording) one half of the information code supplied to buses 15 and arriving at the inputs of the elements, the polling signal is recorded into the drive using the forward address code, and the second half of the information code The incoming at the inputs of AND gates 11 through interrogation signal, delayed element 12 is recorded in a storage medium according to the inverse address code. In the read mode, the bus 17 is given a signal permitting the read. In this case, the interrogation signal reads one half of the information code recorded with the direct address code, and after element 12 also delays the second half of the information code recorded with the inverse address code.

The proposed device has great potential. It provides storage of both an information code with the number of bits not exceeding the number of bits of the accumulator and the information code whose number of bits exceeds (not more than 2 times) the number of bits of the accumulator. In this case, the storage capacity is used efficiently.

The effect obtained is achieved with minimal hardware and time costs. Significant hardware costs are not required for additional bit matching blocks of inputs and outputs of the device with drive input and output tires, which occur with increasing drive royalties for recording a multi-bit code, does not require significant time costs for changing the address code in the address code sensor having place when using a small-size storage device to record a multi-bit information code by dividing the information code into parts and recording each part of the pattern of the generated code at the address in the address code sensor.

Claims (1)

Invention Formula A memory device containing a drive, one of the inputs of which is connected to the outputs of the OR elements, the other inputs of the storage device are connected to the outputs of the address decoder, the inputs of which