SU429466A1 - STORAGE DEVICE - Google Patents

Description

one

The invention relates to the field of computer technology and can be used in the storage devices (memories) of digital computers.

In the known memory, two clock cycles are needed to access the memory cell: the read cycle (when writing information in this cycle, the memory cell is nullified) and the write cycle (reading the information from the memory in this cycle restores the contents of the memory cell). In some cases, for example, when using a memory device as a buffer, recovery of the read information is not required and, therefore, to increase the effective speed, the linking mode is used without regeneration.

However, in such storage devices, when writing information to a memory cell, from which information was previously read without regeneration, the already free cell is reset once again.

The aim of the invention is to increase the effective speed of memory by eliminating the read cycle when writing information to a free memory cell. This is achieved by adding to the storage unit a bit storage storing information on the memory cell occupancy and using a special memory accessing algorithm. In read mode without regeneration, this bit is written O, and on any other access to the memory, this bit stores 1. The write cycle begins with a write cycle and, if the additional bit stores O, consists of one write cycle. If, however, the extra bit is stored 1, then after the write cycle, a correction cycle is performed, in which the combination is made in those bits where the 0 record is made.

The proposed device differs from the known ones in that it contains an additional bit in the accumulator connected to the input of the additional playback amplifier and the output of the unipolar inhibition current driver, with the output of the playback amplifier connected to the input

a control unit, the output of which is connected to the input of a unipolar inhibition current driver.

The drawing shows a structural diagram of the proposed device.

The device includes a storage device 1 with an additional bit 2, playback amplifiers 3, a playback amplifier additional bit 4, two-pole inhibitor current drivers 5, a single-pole inhibitor current driver 6, a control unit 7, the number 8 register, bit 9 and the bus "Decision recording in one measure 10, address

unit and, communication unit 12, unit receiving and issuing codes 13, numeric 14, address 15 and signal line 16.

The device works as follows.

When writing information to the memory cell in the first cycle - the recording cycle, two-pole shapers 5 are switched on, which prohibit recording 1 in the zero bits of the recorded number. If the memory cell is free due to reading without regeneration during the previous access, then the storage element (GD) of the additional bit 2, which is in the zero state, in the write cycle is re-magnetized and changes to the single state. In this case, at the output of the playback amplifier 4, a signal arises, which, via the "Recording resolution in one clock 10, enters the control unit 7, as a result of which the recording cycle ends after executing the first cycle, and the memory in numeric 14, address 15 and Signal line 16 is connected to other devices. After that, the recorded number is stored in the memory cell, and the additional digit 2 GE is in the unit state.

If, however, the memory cell was reset to zero in the previous access, then the additional digit 2 GE is in a single state. At the same time, in some bits of memory cells can be stored 1, although they must be written 0. In this case, as a result of the execution of the write cycle, the GE of the additional bit 2 will not re-magnify, which will lead to a zero signal at the output of the playback amplifier of the additional bit yes 4. In this case, the control unit 7 forms, following the write cycle, a read cycle, in which the two-pole shapers 5 are fed to the discharge windings of the storage device 1 read inhibit currents in those bits where it is necessary to write 1. O neous 7 generated control signal unit which the bus "read prohibition of additional discharge 9 is input unipolar current driver prohibition 6 and turns it on. Turning on the generator 6 prohibits the reversal of the extra-discharge ZE to the zero state, as a result, the required number is stored in the memory cell, and the additional discharge-2 GE is in the unit state.

Reading information with and without regeneration produces 1c as well as

known devices. A read without regeneration is carried out in one step — a read stroke, after which the cell is pa-m; These zeroes, and the extra digit 2 ZE is in the zero state. Reading

regeneration takes two clocks. In the first cycle — the read cycle — information is read out, and in the second cycle — the write cycle — the regeneration (recording) is performed. The memory cell is then stored.

the initial information, and the additional digit 2 GE is in a single state.

Subject invention

A memory device containing a drive connected to the outputs of two-pole inhibition current formers, with playback amplifiers and an address unit, a control unit connected to the two-pole inhibition current formers, with audio amplifiers and a register of the number, the output of which is connected to the reception unit and issuing codes, and a communication unit connected to the address block, characterized in that, in order to increase speed, it contains an additional bit connected to the input of the playback amplifier in the storage device tim additional discharge outlet and unipolar current driver prohibition, the output of amplifier reproducing the additional discharge is connected to a control unit, whose output is connected to the input unipolar current driver za1P1reta.