SU1022216A1 - Device for checking domain storage - Google Patents

Description

torus, the output of which is connected to the first inputs of the eighth and ninth elements And, the second input of the eighth element And is connected to the output of the recording trigger, and the output - the input form

the recording body, the second input of the ninth element I is associated with the output of the read trigger, and the output with the third input of the first control trigger.

The invention relates to computing and can be used to test and control the storage devices of digital computers on cylindrical magnetic domains of a CMD. A storage device with blocking of defective storage elements is known, containing an address register connected via the address decoder to the main accumulator, a word register connected to the first control unit, the main and additional accumulators, the forwarding unit of the faulty groups of bits connected to the address register, the register words, additional accumulator and counter, control unit, coding unit, AND, OR elements, second control unit. The device has an increased reliability as a result of blocking However, it does not provide for the formation of various codes for their writing and comparing the read information with the originally recorded one in the memory check cycle. The closest to the proposed is a memory device with blocking of defective storage cells, containing the first address register connected via a decoded address to the drive connected to the number register, the second address register, the control unit, the additional register, the comparison and counting circuit .2.,. The known device has comparative simplicity and increased over the hedgehog due to blocking faulty cells whose addresses can be written to the drive, but it does not provide for the sequential recording of various information into the drive and then comparing it with the readable information 8 in one drive check cycle . 3, this device has no blocks that provide blocking of the entire device with fixing faulty addresses and bits. These shortcomings are especially significant when checking and monitoring sequential storage devices (such as devices on cylindrical magnetic domains, where information is written and read most often on one channel (the discharge and the monitoring time even for the same code; very significant. Automatic verification It is practically impossible to control and block faulty addresses using all the hard codes in such a device, resulting in the reliability and reliability of the control of memory blocks (especially domain memory). become low, which degrades the reliability of digital computers in which these units are used. The purpose of the invention is to increase the reliability of a device for monitoring domain memory. The goal is achieved by having a device for monitoring domain memory containing two counters, triggers for writing and reading, connected to the code bus Installation O and, respectively, with the code buses. Record and Read, the write driver, the output of which PUE is the device output, and the number trigger, contains the switch, the first input is The second input is connected to the zero potential bus, the comparison unit, the first input of which is connected to the number trigger, the first control trigger, the first input of which is connected to the Start code, the second input to O, and the code bus The output setting is with the second input of the control unit, the second control trigger, the first input of which is connected to the comparison unit, and the second input is connected to the code bus Installation O, the AND and OR elements, and the first inputs of the first and second AND elements to go out the second input of the first I element; to the code bus; Start; the output of the first I element — to the input of the first counter, the first output of which is connected to the second input of the second And element, the output of which is connected to the input of the second counter, the first output of which connected to the first input of the third element And the second output with the first input of the fourth element And, the third output with the second input of the third element And the first input of the fifth element And, the fourth output with the second input of the fourth element And and the first input of the sixth element And, the second output of the first counter is connected to the third input of the switch, the second input of the sixth And element, the output of which is connected to the first input of the first OR element, and to the first input of the seventh And element, the output of which is connected to the third inputs of the third and fourth And elements, the third one | the stroke of the first counter is connected to the fourth input of the switch and to the second input of the fifth element I, the output of which is connected to the second input of the first element OR, whose output is connected to the fifth input of the switch the fourth output of the first counter n It is connected to the second input of the seventh element And, and the fifth and sixth outputs to the sixth and seventh inputs of the switch, the outputs of the third and fourth elements And are connected to the first and second inputs of the second element OR, the output of which is connected to the eighth input of the switch, the output of which is connected the first inputs of the eighth and ninth elements are And, the second input of the eighth element And is connected to the output of the recording trigger, and the output is connected to the input of the recording device, the second input of the same element And is connected to the output of the reading trigger, and the output from the third input control trigger. The proposed device allows you to write all kinds of codes to the domain memory CB (including all heavy codes), read information from the drive and automatically compare it with what was recorded. In this case, the faulty information and the address are recorded both at the address of the recorded page (the address of the group of words) and at the address of the tact (the address of the discharge word in the group of words). The drawing shows the block scheme of the proposed device for. control of domain memory. The device for controlling the domain memory contains the first and second counters 1 and 2, triggers 3 records and k readings connected to the code bus Installing O and, respectively, to the code buses Write and Read, the imaging unit 5 connected to drive 6 on the NMD connected to readout amplifier 7, associated with the trigger number 8. In order to increase the reliability and reliability of the domain memory control, the switch 9, the comparison block 10, the first control trigger 11, the second control trigger 12, nine AND 13-21 elements and two OR 22 and 23 elements are inserted into the device. The device operates as follows. Initially, the signal M sets all blocks and elements of the device to their initial state (first, trigger 3 records, read trigger, first 11 and second 12 control triggers. After that, the device receives a Start signal, which, in the absence of an inhibit potential, with three | - Hera 12 through the first element And 13 passes to the first counter 1 and then through the second element And l to the second counter 2. The first 1 and second 2 counters form the entire time diagram of the operation of accumulator 6 on the CMD, including the creation of a rotating magician But this does not exhaust the functions of the first 1 and second 2 counters. Using the third, fourth, fifth, sixth and seventh elements I 15–19 and the first 22 and second 23 elements OR they form various codes for recording information into the drive 6 on the CMD and to control information when it is read out from drives 6. These codes go to switch 9, having as many inputs as there are codes in the device, and one output connected to inputs of the eighth 20th and ninth 21 elements I. From the power supply through the switch to implement L is a record of all 1 and all G in the storage unit 6 in CMD. Signals taken from the first bit of the first counter 1 (clock counter) on the second and third outputs (.. the direct and inverse outputs are recording the forward and reverse chess codes in the storage register of the accumulator 6. Signals taken from the third bit of the first counter 2 on the fifth and sixth outputs, allows to write 6 forward and reverse codes of the moving three 1 and three O into the memory register Fifth 17 and the sixth 18 elements AND and the first element OR 22 to write to the drive forward and reverse codes in storage registers phone using the third 15, fourth 1b and seventh 19 And elements and the second element OR 23 is forming a record of the moving three 1 and one O and vice versa in the storage register of the drive 6. The formation of different codes can be extended by using different combinations of elements AND and OR and connecting them to different bits of the first and second counters 1 and 2. In the recording mode, after setting the trigger on 3 for 3 records with a signal, setting O and starting the first counter 1 L of the clock counter) and the second counter 2 (page counter t The recording rigger 3 is set to 1 signal Record, and in the corresponding clock cycles from the switch 9, the code write pulses defining a particular code will pass through the eighth element AND 20 to the recorder 5 and record this code into the accumulator 6. In this case, the recording can be carried out both in a particular page of drive 6, and in the weight of the drive. When switching to read mode, due to the absence of a signal, write 166 pulses from switch 9 will not go through to start writing 5, but at the same time, when the signal is read, read read trigger k is set to 1, allowing passage of certain pulses from switch 9 to certain cycles through the ninth element I 21 to trigger the trigger 11, which is set to O at the beginning of each clock cycle. If the signal 1 comes from the switch 9, the first trigger 11 is set to 1, if there is no signal O, then it remains in O. At the same time, in certain cycles of the common cycle from accumulator 6, information is read which, after amplification in the 7 readout amplifier, arrives at the trigger of 8 numbers, setting it in each step to 1 or O stage. recorded in accumulator 6 and now arriving at the first additional trigger 11, and the information read from accumulator 6 and now arriving at the trigger 8 numbers are compared at block 10 of the comparison. If these two informations are identical, the information is read in the next clock cycle. Otherwise, the incomparable signal sets 1 trigger 12, which blocks the operation of 1 and 2 second counters, fixing the number of the faulty page (group of words) in drive 6 and the cycle number (the bit in this group of words; thus, using the invention automatically generate various heavy write codes to the drive on the CMD (both in the entire drive and in separate pages), then poll the drive and automatically compare the recorded and read signals, which significantly increases the reliability and accuracy of control domain memory, increasing the overall reliability of the test and control memory of digital computers devices.

"

r /

f

Ni

I

/ k f

iS

t. I

ff // ff / 9 / ffAJ

, 0

"Vl

Ni / L L

"

  V7 G7 g

 r7v

Claims (1)

DEVICE FOR DOMAIN MEMORY CONTROL, containing two counters, write and read triggers connected to the code bus Setting 0 and, respectively, to the Write and Read code • buses, a write shaper whose output is the 'device output, and a number trigger, characterized in that, in order to increase its reliability, it contains a switch, the first input of which is connected to the positive terminal of the power source, the second input is to the zero potential bus, a comparison unit, the first input of which is connected to the number trigger, the first th control trigger, the first input of which is connected to the start code bus, the second input to the code bus Set 0, and the output to the second input of the comparison unit, the second control trigger, the first input of which is connected to the comparison unit and the second input to the code bus Setting 0 , AND and OR elements, with the first inputs of the first and second AND elements connected to the output of the second control trigger, the second input of the first AND element to the code bus Start, the output of the first AND element to the input of the first counter, the first output of which is connected to the second entrance of the second element And, the output of which is connected to the input of the second counter, the first output of which is connected to the first input of the third element And, the second output - with the first input of the fourth element And, the third output with the second input of the third element And the first input of the fifth element And, the fourth output is with the second input of the fourth AND element and the first input of the sixth AND element, the second output of the first counter connected to the third input of the switch, the second input of the sixth AND element, the output of which is connected to the first input of the first OR element, and the first input of the seventh AND element, whose output is connected to the third inputs of the third and fourth AND elements, the third output of the first counter is connected to the fourth input of the switch and to the second input of the fifth AND element, the output of which is connected to the second input of the first OR element, the output of which is connected to the fifth input of the switch, the fourth output of the first counter is connected to the second input of the seventh element And, and the fifth and sixth outputs are connected to the sixth and seventh inputs of the switch, and the outputs of the third and fourth elements | M are connected to the first and second inputs: the second OR element, the output of which is connected to the eighth input of the commutator 1022216 of the torus, the output of which is connected to the first inputs of the eighth and ninth elements AND, the second input of the eighth element And is connected to the output of the recording trigger, and the output - by the input of the recording writer , the second input of the ninth AND element is connected to the output of the readout trigger, and the output to the third input of the first control trigger.