SU780042A1 - Logic storage - Google Patents

Description

outputs, decoders4 addresses, regis 5 addresses, the first 6,1-6,4 and the second

7groups of elements And, the first register

8 words, with direct 9 and inverse 10 outputs, the third group of elements and 11, elements OR 12.1 and 12.2, the second register 13 words, the control bus 14-18.

The address inputs of the address decoders 4 are connected to the outputs of the address register 5, and the outputs to the inputs of drives 1. The first inputs of the AND elements of the first group 6.1-6.4 are connected respectively to the control buses 15-18, the second inputs to the outputs of the second register 13 words, and outputs - to the inputs of the elements YALI 12.1 and 12.2.

The direct outputs 2 of the accumulators 1 are connected to the first inputs of one of the elements 11 of the third group, and the inverse outputs the 3rd to the first inputs of other elements of the 11 11 of the third group. The outputs of the elements OR 12.1 and 12.2 are connected to the second inputs of the elements And 11 of the third group, the outputs of one of which are connected to the inputs of the installation in 1 of the first register 8 words, and the outputs of others with the inputs of the installation in About the first register of 8 words.

The first inputs of the elements of the second group 7 are connected to the control bus 14, and the outputs are connected to the information inputs of the drives 1. The second inputs of one of the elements of the second

Groups 7 are connected to the direct outputs 9 of the first register of the word 8, and the second outputs of the other elements AND of the second group 7 to the inverse outputs 10 of the first register of the 8 words.

The analysis of the device operation can be performed by representing it as an elementary automaton with two inputs, the transition function of which, taking into account the control signals, has the form:

tVi (, a) (rvrvr Vr) v. (t) (i-, v -2XVK-,

where (t + 1) is the state of the element

memory at time (t +1); q ,. (t) is the state of the memory element at the moment of time (t);

control signals to

. control tires 15, 16,17,18.

X - binary variable, recorded in the register 13 words.

Implemented by such an elementary automaton: ;; ical operations between a variable, X, recorded in word register 13 and a variable Y, recorded in the selected memory cell, under different initial conditions and combinations of control signals obtained from this expression, are given in table. where P is the signal at the output of the element OR 12.1., k is the signal at the output of the element OR 12.2.

The operation of the device is based on the example of the implementation of a logical operation modulo 2 sum between two binary variables K, recorded in word register 13, and Y, recorded in the selected cell of drive 1. The result of the operation is written in place of the variable} (.

For this, during a clock pulse on control tires 16 and 13

and bus 14, through which the write enable signal is received, it is necessary to set the signals to zero and, on the control buses 15 and 17, to have a single signal value. At the same time, through the elements AND 6.1 and OR 12.1 a signal repeats the variable X, and through the elements 6.3 and OR 12.2 passes a signal repeating the inverse value of the variable X. Depending on the value of the variable K, i.e., from the state of the selected memory location and, therefore, the forward 9 and inverse 10 outputs of the accumulator 1 register 8 words through the elements 11 of the third group, the function X, ®Y is recorded

At the end of the clock pulse, in a pause, a single signal value is supplied to the control bus 14 (recording resolution), and zero to the control bus 15,16,17,18. This allows the contents of register 8 to be rewritten into the selected cell of accumulator 1.

The result of the operation is obtained in the selected cell of accumulator 1 to the beginning of the next clock pulse. Thus, the operation is performed in one call to drive 1.

The feasibility of the proposed device lies in the fact that it ensures the implementation of each logical operation in a single access to the drive, thereby improving the speed of this logical storage device.

Claims (2)

1. USSR author's certificate number 477464, cl. G 11 C 15/00, 1974. 2. The author's certificate of the USSR 501421, cl. G 11 C 15/00, 1974 0 (prototype). ..