SU533983A1 - Memory device - Google Patents

Description

Information selection is connected to the second output of the address register, the third input of which is connected to the first output of the information selection block, the second output of which is connected to the input of the address decoder, the third output of the information selection block is connected to the second input of the word register, the third input of the information analysis block is connected to the fourth the output of the information selection unit, the fifth output of which is connected to the outputs of the storage device, the third outputs of which are connected to the third input of the information selection unit.

The drawing shows the functional} and the storage device.

The memory device consists of address register 1, accumulator 2, address decoder 3, information analysis block 4, control block 5, information select block 6, word register 7, control bus 8, information bus 9.

The storage device operates as follows.

In the register of address 1 through the information bus 9 enters the address of the word that must be read or written, or the address of the first word and the number of words in the array when writing and reading the array.

The address of the word consists of four parts; Addresses A1 words in a line; A2 addresses of the zone where the word is located; A3 addresses of the words in the zone; Am numbers of words in the array.

The part of register 1 where Am is sent is in the form of a subtracting counter. In the information selection block, from the address A3, the contents of the current address counter are subtracted, the value of which increases by one for each shift signal on the control spike 8. The result of the subtraction goes to the executive address counter of the information selection block 6 and with a positive subtraction result, i.e. in the sign bit position, shift pulses are received at the subtracting input of the counter of the executive address. In information selection block 6, the address A2 is subtracted from the contents of the current zone number counter. When the contents of the counter of the executive address of the information selection block 6 become equal to "O", the enabling signal is received and the address A is fed to the decoder of the information selection block 6. From the output of this decryptor, the address A1 is fed to the register of the information selector b.

Subsequently, in the information selection block 6, the results of actions by the address are compared with m (where m is the number of outputs of the decoder 3) and with a negative result, a positive number is assigned to it according to the rule:, -,, ... -t-1 and compared with T. Decoder

Address 3 is selected, the output line of drive 2 is needed.

When Am becomes equal to zero, one of the triggers of information selection block 6 is set to "O" and the signal "Reset is issued, and

the control unit 5 generates a signal "End of operation. The control unit 5 synchronizes the operation of all elements: information selection unit 6, information analysis unit 4, controls the operation of accumulator 2, address register 1, word register 7.

Thus, the proposed storage device performs the same functions as the known one, but with a slight increase in hardware, it achieves a speed of 30-60 times more than the known one, which leads to an increase in its efficiency relative to the prototype by about the same amount.

Claims (1)

Invention Formula A memory device containing a packer, the first inputs of which are connected to the outputs of the address decoder, the second inputs of the storage device are connected to one of the outputs of the control unit, the other output of which is connected to the first input of the word register, the third output of the control unit is connected to the first input of the address register, the first output of which is connected to one of the inputs of the information analysis unit, the other input which is connected to the control bus, and an information bus connected to the second input of the address register, characterized in that, in order to improve speed, an information selection unit is entered into it, the first in Which is connected to the output of the information analysis unit, the second input of the information selection unit is connected to the second output of the address register, the third input of which is connected to the first output of the information selection unit, the second output of which is connected to the input of the address decoder, the third output of the information selection unit is connected to the second input the word register, the third input of the information analysis unit is connected to the fourth output of the information selection unit, the fifth output of which is connected to the accumulator outputs, the third inputs of which are connected to the third input of the information selection block.