SU551702A1 - Buffer storage device - Google Patents

Description

(54) BUFFER STORAGE DEVICE

The known buffer memory device contains the first registers connected in bits, the control and writing and writing cells, the logic elements I. The disadvantages of the known device are low operation speed and high hardware costs. Closest to the invention, a buffer memory device that contains n registers, the same type bit buses of which are connected in series, the register entry inputs, except the first, are connected to the outputs of the AND elements, n triggers whose output elements are connected to the bit outputs of the nth register and The nth element of AND, and the bus clock impulses. However, this device has a low speed, since the control is performed according to a multi-cycle scheme, and the registers are executed on triggers with passive writing. The purpose of the invention is to increase the speed of the device. This is achieved by the fact that the buffer memory device contains n elements OR of the first group {1Y, n - 1 element OR of the second group, elements NOT according to the number of even registers, single outputs of the flip-flops are connected to the first inputs of the same-name elements OR of the first group, zero outputs of the flip-flops, except of the first, to the first inputs of the same-named elements OR of the second group, the outputs of the elements OR of the first group are connected to the first inputs of the elements of the same name AND, the outputs of the elements OR the second group of connections: with the second inputs of pre-search elements And, the outputs of the elements And are connected to the second inputs of the elements of the same name OR of the first group and, besides the P - GO element AND, to the second inputs of the subsequent elements OR of the second group, the third in the networks of odd elements AND connectors with the bus pulse pulses connected through the elements NOT to the third inputs Four elements I. The drawing shows the scheme of the proposed device. The device contains n registers 1, whose same-named bits are connected in series, n flip-flops 2, elements OR 3 of the first group, n-I elements OR 4 Bts1X groups, n elements AND 5, elements HF-, 6 by the number of even registers

1, the bus 7 clock pulses, the bus 8 records information.

Single outputs of the flip-flops 2 are connected to the first inputs of the same-named elements OR 3 of the first group, zero outputs of the flip-flops 2, the crO of the first one (top in the drawing). - to the first inputs of the same-named elements OR 4 of the second group, the outputs of the OR 3 elements of the first group are connected to the first inputs of the same element And 5, the outputs of the elements OR 4 of the second group are connected to the second inputs of the previous elements And 5.

The outputs of the elements And 5 connected to the second inputs of the same elements OR 3 of the first group and, in addition to the n-th element AND (lower in the drawing), to the second inputs of the subsequent elements OR 4 of the second group, the third inputs of the odd elements And 5 are connected to bus 7, connected through the elements NOT 6 to the third inputs of the even elements I 5. Bus 8 is connected to the input of the first trigger 2, and bus 9 is connected to the input of the last element I 5 - the information from the bus 9. The device also contains output elements AND 10 for outputting information and an input register 11.

The device works as follows.

On bus 7, clock pulses whose frequency is not lower than the frequency of information recording are constantly gessed. To write information to a memory device, a bus enters the bus 8, through which the first word is written to the register I, and simultaneously the first trigger 2 is set to one state. The unit potential from the output of the first trigger 2, the passage through the first element OR 3, opens the first element AND 5 through the first input. And the second input element AND 5 at this moment is opened with potential from the element OR 4. The pulse. Pulse, the first element AND 5, sets the first trigger 2 to the zero state, and the second trigger 2 to the unit one and rewrites the information from register 11 to the first register 1. On the falling edge of the clock pulse, the second element AND 5 triggers, the second trigger 2 sets to the zero state, the third trigger 2 - in one e, and the word from the first register 1 is rewritten to the second register 1.

Further promotion of information from the register to the register is carried out similarly.

Feedback between the elements of AND 5 and the elements of OR 3 and 4 prevents clipping of the pulses at the exit of the elements of AND 5, obechechiva

reliable rewriting of information from the register to the register and the installation of the flip-flops 2; Through the clock pulses (where n is the number of registers 1), the first word will appear in the last, n-th register.

When information is obtained, a pulse is fed to the information reading bus 9 and the first word is passed from the device through the elements of AND 10. If the next register 1 is occupied, the signal from the zero output of the trigger 2 is received through the same name

the element OR 4 at the input of the element AND 5 of the previous bit, block rewriting information in this register. When releasing the subsequent register, the corresponding trigger is reset and unlocked the And 5 element, which serves to overwrite information from the previous register.

On the leading edge of the clock pulse, information is copied from even register 1 to odd; on the falling edge, information is rewritten from odd register 1 to even.

Claims (1)

Invention Formula A buffer memory device containing n registers, the same-named bit terminals of which are connected in series, and the register entry inputs, except for the first, are connected to the outputs of the AND elements, n triggers, the output elements of AND, whose inputs are connected to the binary outputs of the n-th register and th element, and clock bus, characterized in that, in order to increase speed, it contains n elements OR of the first group, n-1 elements OR of the second group, elements NOT by the number of even registers, single outputs of the flip-flops are connected The first inputs of the same-named elements OR of the first group, zero outputs of the flip-flops, except the first, are connected to the first inputs of the same-named elements OR of the second group, the outputs of the OR elements of the first group are connected to the first inputs of the same elements AND, the outputs of the OR elements of the second group are connected to the second inputs of the previous AND elements, the outputs of the AND elements are connected to the vyurp "inputs of the same elements OR of the first group and, in addition to the n-th element AND, the second inputs of the subsequent elements OR of the second group, the third inputs of the odd elements AND connected to the clock pulse, connected through the elements NOT to the third inputs even elements I.