SU1479941A1 - Unit for editing data in table - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase speed. The device contains a counter 1, a memory block 2, two registers 3.12, a decoder 10, a reference element 11, a group of 5 And elements, a prohibition element 6, three delay elements 8,9,24, a generator of 7 clock pulses, four And 4 elements , 18,20,21, element IS-NE 19, two triggers 22,23 and inverter 25. The invention can be used in systems for managing relevant databases. 2 Il.

Description

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The invention relates to computing and can be used in a system for managing relevant databases.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the device.

The device contains counter 1, memory block 2, register 3, element 4, group 5 of elements I, prohibition element 6, clock generator 7, delay elements 8, 9, decoder 10, comparison element 11, row register 12, address input 13 devices, information input 14, mode setting input 15, start input 16, device information output 17, AND element 18, AND-NE element 19, AND elements 20, 21, triggers 22, 23, delay element 24, inverter 25.

Memory block 2 contains a number of tables. The row of the table occupies one memory location. All lines have a key field. In each table, rows can be sorted (to speed up the search for the desired row) in ascending or descending order of keys. The cell of memory block 2, immediately following the last row of the table, records the end of the table code (unique code) decoded by the decoder 10.

The device works as follows.

In the initial state, generator 7 is inhibited. In counter 1, from input 13, the pulse at input 15 records the address of the first row of the table in which any row must be replaced, and simultaneously with this pulse, the triggers 22, 23 are reset. The replacement string is entered into register 12 from input 14. The device is ready for operation.

Replacing a row in the table is initiated by a pulse on input 169 which starts generator 7. On the first pulse from its output, the first row of the table is received in register 3. The decoder 10 does not signal, and trigger 22 is in the initial state, therefore prohibition element 6 is open. If the key of the read string does not match the key of the replacing row, then the comparison element 11 does not signal and the AND elements 4, 21 are closed. Pos

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five

five

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0

five

After this, a pulse appears at the output of the delay element 8 and through the open element I 20 enters the input of the element 9-delay and the information input of the prohibition element 6, and from it the input of the group 5 of the elements I. The group of 5 elements opens AND, and the first line the tables from register 3 is outputted to output 17. Then a pulse appears at the output of delay element 9, according to which the contents of counter 1 are incremented by one, since the address of the second row of the table is generated. On the second pulse from the output of the generator 7, the second row of the table is received in register 3, analyzed by the reference element 11, output 17 is output, and in the counter 1 the address of the third row of the table is formed. Reading and issuing rows in a similar way occurs as long as the key field of the read string does not coincide with the key field of the replacement string. Coincidence means that the line is found. When the keys coincide, the comparison element 11 opens element 21 and the signal from the output of which opens element 4 and through inverter 25 closes element 20. The pulse from the output of delay element 8 through the open element 4 enters the recording input of memory block 2 and writing the replacement string from register 12 to the memory block at the address specified on counter 1, i.e. in the cell where the replacement line was. Then, a pulse appears from the output of the delay element 24, is fed to the installation input to the unit of the trigger 23, which is thrown, locks the AND 21 element and opens the AND 18 element. And the 21 element locks And 4, in turn, and the inverter 25 opens element AND 20. The next row from generator 7, the corrected table row from memory block 2 is received in register 3. The signal from the comparison element to the AND 4 element and the inverter 25 does not pass, because And 21 is closed by a signal from the trigger 23. After that a pulse appears at the output of element 8 delay and through the open element 20 And the element 6 of the ban enters the input of group 5 of the elements I. It opens, and the corrected row of the table from register 3 is output to output 17. Then a pulse appears at the output of the delay element 9, which enters the input of the element And 18, the signal from the output of which overturns the trigger 22. The signal from the output of the trigger 22 through the element IS-NOT 19 closes the prohibition element 6 and sets the generator 7 to the forbidden state.

The device allows to implement a read-only mode, if a string with a key that certainly does not have one row of the table, is written into the register of a string. In this case, the replaced row will not be found and there comes such a moment when, according to the next pulse from the output of the generator 7, the end of the table code is received in register 3. In this case, a signal appears at the output of the decoder 10, which closes the prohibition element 6 through the element IS-HE 19. The contents of the register 3 to the output 17 is not received. By the same signal, the generator 7 is set to the forbidden state.

A new cycle of operation of the device begins after updating the contents of counter 1, register 12, setting the triggers 22, 23 to the initial state and applying a pulse to the input 16.

The time of the prototype when adjusting the rows in the table

K-p

fT.r (n + 1) ..., (1)

- frequency of the clock generator;

- the number of rows in the table.

work proposed device

K. p.

 fT.r (i + 1) ..., (2)

where i is the location of the line in

the table.

Proceeding from the fact that the search for a row in the table is carried out sequentially, and the average time for a sequential search is 1 + n / 2 (for large n it will be n / 2), it can be concluded that the speed of the device will increase by an average of 2 times.

Claims (1)

Invention Formula A device for editing entries in tables containing a memory block, an AND element, a counter, a register, an AND group of elements, a prohibition element, clock generator, two delay elements, decoder, reference element, row register, the clock pulse start input is the device startup input, the clock pulse output is connected to the read input of the memory unit and through the first element The Q delay is connected to the first input of the element I, the output of which is connected to the recording input of the memory block whose output is connected to the information input of the register whose outputs 5 is connected to the information inputs of the decoder and the inputs of the group of elements AND of the group whose input is connected to the output of the prohibition element, the outputs of the elements AND of the group are information outputs of the device, the information inputs of the string register are of the same name as the device inputs, the output of the string register is connected to the first information input the comparison element and the information input of the memory unit, the register outputs are connected to the second information input of the comparison element, the information input of the counter is addressable m The Q input of the device line, the mode setting input of which is connected to the counter recording input, the output of which is connected to the address input of the memory unit, the counter count input connected to the output of the second delay element, characterized in that, in order to increase speed, two triggers are entered into it , three AND elements, an inverter, an NAND element, a third delay element, and the device mode setting input is connected to the installation inputs in O of the first and second triggers, the output of the second delay element is connected to the first input of the second element, AND, The output of which is connected to the input, installation in 1 of the first trigger, the output of which is 5 0 five It is connected to the first input of the NAND element, the second input of which is connected to the output of the decoder, and the output is connected to the inhibit input of the delay element and the stop input of the clock generator, the output of the first AND element is connected via the third delay element to the installation input 1 of the second trigger, the direct output of which is connected to the second input of the second element I, the inverse output of the second trigger is connected to 71479941g the first input of the third element And, i delay element, the output of the fourth the output of which is connected to the second input element And is connected to the input of the second the house of the first element And and through the in-element delay and information the vert is connected to the first input of the even-input of the prohibition element, the output of the element A, and the second output of the comparison module is connected to the second the second is connected to the output of the third element I.