RU2001451C1 - Associative storage device - Google Patents

Description

The invention relates to computer technology, in particular to storage devices, and can be used in specialized storage systems and digital image processing, in associative parallel processors, in solving information and logic problems, tasks of searching and sorting data, in digital signal processing devices in real time scale.

Known associative storage device containing a matrix drive, the first register of polling and masking data, the first and second decoders, the first, second, third and fourth groups of AND elements, the first and second groups of OR elements, the first and second groups of inverters, the first and second extraction blocks a multi-valued response, a control unit and a second register for storing output information.

The disadvantage of this device is the lack of performance due to the inability to conduct parallel associative search simultaneously in the rows and columns of the matrix associative drive.

The closest technical solution to the inventive device is an associative storage device containing an associative drive, an address decoder, a block of data polling and masking registers, first and second reaction commit registers, first and second multiple match analyzers, first and second encoders.

The disadvantage of this device is its insufficient performance due to the inevitable rewriting of the mirrored search argument into the block of polling and masking registers during the associative data search in case their orientation in the associative drive is unknown.

The aim of the invention is to expand the scope of the device by making it possible to carry out an associative parallel masked search for the same search argument, presented both in direct and in mirrored form, without overwriting it in the block of polling and masking registers, simultaneously along the lines and associative drive columns.

The goal is achieved in that in an associative storage device containing an associative matrix storage device, an address decoder is a block of polling and data masking registers, the first and second reaction fixing registers,

the first and second multiple analyzers, the first and second encoders, the address inputs of the address decoder are the address inputs of the device,

the input of the sample is simultaneously the control input of the device, and the outputs are connected respectively to the first interconnected inputs of the memory elements of the corresponding rows of the associative drive, the second and third inputs of the memory elements of the rows of the associative drive are interconnected and connected to the fifth and fourth interconnected inputs

5 memory elements of the columns of the associative drive corresponding to these lines, the first outputs of the memory elements of each row of the drive are also interconnected and connected to the corresponding information input of the first reaction register, whose control input is the record control input of the second register reactions, as well as the control input of the polling and reading of the device, the first group of information outputs is the first group of information outputs of the device, and the second group of information The outputs of this register are connected to the corresponding data inputs of the first multiple-match analyzer, whose strobe input is simultaneously the strobe input of the first encoder and the control input of the device as a whole, the output

5, the state of the first multiple-analyzer is the first output of the device status, and the information outputs are connected to the corresponding information inputs of the first encoder, the outputs of which are the first group of address outputs of the device, the second outputs of the memory elements of each storage column are interconnected and connected to the corresponding information input of the second register of reaction fixation, the first group of information outputs of which serves as the second group of information outputs devices, and the second group of information outputs from the register is connected to the corresponding data inputs of the second multiple analyzer, whose gating input is simultaneously the gating input of the second encoder and the control input of the device as a whole, the state output of the second multiple analyzer is the second output the status of the device, and the information outputs are connected to the corresponding information inputs of the second encoder, the outputs of which are the second group a device outputs, the information inputs of the block of polling and masking registers are the information inputs of the device, and the control inputs are the inputs of writing and resetting the registers of this block, as well as the control signals of recording and polling of the device as a whole, the third and fourth outputs of each group the outputs of this block are connected respectively to the sixth and seventh inputs of memory elements of the corresponding column of the drive, an inverter and groups of OR elements are introduced, and the first and second outputs of each group you The strokes of the block of polling and masking registers are connected to the first inputs of the first and third, as well as the second and fourth OR elements of the corresponding group, the second inputs of the third and fourth OR elements of all groups are connected to the inverter output, the input of which is connected to the control signal for selecting the device polling direction and with the second inputs of the first and second OR elements of all groups, the outputs of the third and fourth OR elements of each group are connected respectively to the fifth and fourth inputs of the element in the corresponding column of the memory storage means, and outputs the first and second OR elements, starting with the first group are connected respectively to the second and third inputs of memory elements of rows of the associative storage means, starting from the last row.

A comparative analysis with the prototype shows that the claimed device is distinguished by the presence of new elements: an inverter and groups of OR elements and their connections with other elements of the circuit.

Comparison of the claimed technical solution with others shows that the proposed device has a new technical property, which consists in the possibility of an associative parallel masking search for the same search argument, presented both in direct and in a mirrored form, without rewriting it in the block of registers of the poll of masking, simultaneously along the rows and columns of the associative drive, not inherent in known objects containing signs that act as differences from prot otipa.

On Fig, 1 presents a diagram of an associative storage device; in FIG. 2 is a diagram of a memory element; FIG. 3 is a diagram of a block of polling and data masking registers.

The device (see, Fig. 1) contains a storage device 1. which includes memory elements 2 with inputs from the first 3 to the seventh 9 and the first 10 and second 11 outputs. The device also contains an address decoder 12, a block 13 of polling and masking registers, the first 14 and second 15 registers of reaction fixation, the first 16 and second 17 analyzers of multiple coincidence, the first 18 and second 19 encoders, the inverter 20, the group of elements OR from the first 21 to the fourth 24.

The address inputs 25 of the address decoder 12 are the address inputs of the device5, and the outputs are connected respectively to the first 3, interconnected inputs of the elements 2 of the memory of the corresponding lines of the associative drive 1, the second 4 and third 5 inputs of the elements of the 2 memory of the lines

0 associative storage devices are interconnected and connected respectively to the fifth and fourth interconnected inputs of elements 2 of the memory columns of the associative storage devices corresponding to these rows. In addition, the outputs of the first 21 and second 22 of the OR elements, starting with the first group of OR elements, are connected respectively to the second 4 and third 5 inputs of the memory elements 2

0 lines of associative storage, starting with the last line.

The information inputs 26 of the polling and masking unit 13 are the information inputs of the device, the first 27 and

5, the second 28 outputs of each group of outputs of this block are connected respectively to the first inputs of the first 21 and third 23, as well as the second 22 and fourth 24 elements OR of the corresponding group. The second inputs of the third 23 and fourth 24 OR elements of all groups are interconnected and connected to the output of the inverter 20, the input of which is connected to the control signal 29 for choosing the direction of interrogation of the device and to the second inputs of the first 21 and second 22 elements OR of all groups,

Fifth 7, fourth b, sixth 8 and seventh 9 inputs of elements 2 of the memory of the corresponding columns of the associative

0 drives are interconnected and connected respectively to the outputs of the third 23 and fourth 24 elements OR of the corresponding group, to the third 30 and fourth 31 outputs of the corresponding

5 groups of outputs of block 13 polling and masking registers.

The first 10 outputs of memory elements 2 of each line of the drive are interconnected and connected to the corresponding information input of the first 14 reaction register, the first group of 32 information outputs is the first group of information outputs of the device, and the second group of information outputs of this register is connected to the corresponding data inputs the first 16 multiple match analyzer. The state output 33 of the first 16 match analyzer is the first state output of the device, indicating the presence of a certain number of matches as a result of a parallel associative search in the lines of the associative drive.

The information outputs of block 16 are connected to the corresponding information inputs of the first 18 encoder, the outputs of which serve as the first group of 34 address outputs of the device.

The second 11 outputs of memory elements 2 of each drive column are interconnected and connected to the corresponding information input of the second 15 reaction fixation register, the first 35 information output group is the second information output group of the device, and the second information output group of this register is connected to the corresponding data inputs of the second multiple analyzer 17. The state output 36 of the second multiple match analyzer 17 is the second state output of the device, indicating the presence of a certain number of matches as a result of a parallel associative search through the columns of the associative drive.

The information outputs of block 17 are connected to the corresponding information inputs of the second 18 encoder, the outputs of which serve as the second group of 37 address outputs of the device.

The following control signals are supplied to the device:

38 - write signal in the drive 1;

39 is a polling and reading signal from drive 1;

40 - write signal to the polling register of block 13;

41 - signal write to the masking register block 13:

42 is a reset signal in O of the polling and masking registers of block 13;

43 - signal selection decoder 12 addresses;

44 - a signal of gating the worked out and sampling of the next active line by the first 16 multiple match analyzer, as well as the first 18

encoders for the first 34 group of address outputs of the device active line addresses; 45 is a signal for gating the worked out and sampling the next active line by the second 17 multiple-analyzer, as well as issuing the second 19 encoder to the second 37 group of address outputs of the device of the active line address.

In FIG. 2 shows an example of the implementation of memory element 2, consisting of RS flip-flop 47 with inverse inputs of the set to 1 (S) and O (R) and elements I – H E from the first 47 to the sixth 52. FIG. 2 also does not show shown in FIG. 1 restrictive elements 53, 54, 55 and 56 in the form of resistors, 57 - output logical units.

In FIG. 3 shows a data polling and masking unit 13 comprising a register

58 question and register 59 masking, the first 60 and second 61 groups of inverters, the first 62 and second 63 groups of elements I.

The device can operate in the following modes: recording information at a given address with masking arbitrary bits of the recorded word; reading information on rows and columns in direct and inverse code; conjunctive reading of rows and columns of the drive; parallel associative search of the same search argument, presented both direct and in a mirrored form, without overwriting it in the polling and masking register block, simultaneously along the rows and columns of the drive.

In the recording mode, before the signal 38 is written to the drive 1, the polling register 58 of the input block 13c of the inputs 36 records the search argument by the signal 40. Then to register

59 to mask the same block, a mask is recorded by signal 41 (units in the bits of the mask register 59 determine the masking of the corresponding bits of drive 1). Then, the n-bit address of the string is supplied to the inputs 25 of the address decoder 12.

n log2N,

where N is the bit depth of drive 1 in rows and columns.

Log level is applied to control input 29. 1, which gates the signals from the outputs of the first 21 and second 22 elements OR of all groups. And when the signal 38 and the address are decoded by the address decoder 12 by the signal 43, one of the following signal combinations comes from the outputs of the third 30 and 31 of each group of block 13 to the inputs 8 and 9 of all memory elements 2: 10 - unit recording code, 01 - write code is zero

00 is a masking code; and the active level log is applied to the inputs of 3 elements 2 of the memory of the drive line to be activated. 1. And thus, recording is made at the selected line address.

When an i-ro word is read in the direct code from the drive, the polling register 58 of block 13 registers the argument with the unit in the 1st bit by signal 40. Then, mask mask masking everything is entered into mask masking register 59 by signal 41 except for the 1st, bits of the argument. And when a polling and reading signal 39 is supplied to the device with a unit at input 29, inputs 4 and 5, as well as 7 and 6 of memory elements 2, respectively allocated rows and columns of the drive, receive a combination of signals 10. In this case, the read word is written in the second 15 is a register for fixing reactions and is output to the second group 35 of information outputs of the device. At the same time, the first bit section is recorded in the first 14 register of reaction fixation, which is output to the first group of 32 information outputs of the device.

When reading in the inverse code, in the 1st bit of the polling register 58 of block 13, zero should be written, ceteris paribus.

In conjunctive read mode, an argument is written to the polling register 58 of block 13 with units in bits corresponding to the word being read. Then, a mask is entered into the masking register, masking all but the indicated bits of the argument. And with a unit at input 29, when the read signal 39 is supplied to the device, the results of conjunctive reading of respectively selected bit sections and highlighted words are recorded in the first 14 and second 15 reaction registers (see the simple read mode). In the event that zeros are written in the unmasked bits of the polling register 58 of block 13, the conjunction will be performed with the inverse codes of the corresponding rows and columns.

In the mode of parallel associative masked search of the same search argument, presented in direct form, at the same time by rows and columns on the control input 29 of the sample selection of the device polling direction, logical level 1 should be set (as in all the above modes). The search argument by signal 40 is written into register 58 of block 13. Then, a mask by signal 41 is entered into register 59 of this block. And when the reading signal 39 is supplied to the device, it must be connected to inputs 4 and 5 (inputs of a column poll), as well as to inputs 7 and b (line-by-line polling inputs) of memory elements2, one of the following signal combinations arrives: 10 - comparison with unity, 01 - comparison with zero, 00 - masking of comparison. The results of the row and column associative searches are recorded respectively in the first 14 and second registers of reaction fixation by signal 39. Moreover, if you display words or bit sections that match the masked search argument, then the corresponding bits of the corresponding reaction fix registers are set to one .

The first 16 multiple match analyzer serves to prioritize one of the active lines of the first 14 of the reaction fixation register. In this case, the argument with the zero address has the highest priority of the arguments.

The address of the active line selected by the first 16 multiple-analyzer is encoded by the first 18 encoder and is output to the first 34 group of address outputs of the device by signal 44. By re-supplying this signal, the worked-out and initialization of the next active line by the first 16 multiple-match analyzer is constructed.

All of the above about the first 16 multiple match analyzer and the first 18 encoder is valid for the second 17 multiple match analyzer and the second 19 encoder in their own context.

In the mode of associative parallel masked search of the same search argument, presented in a mirrored form, without overwriting it in the block of polling and masking registers, simultaneously along the rows and columns of the associative drive, at the control input 29 of choosing the polling direction of the device should be set logic level to zero. In this case, when signal 39 is applied, signs of comparison with unit 10, zero exhaust gas, or signs of comparison masking are removed not from the outputs of the third 23 and fourth 24 OR elements of all groups, but from the outputs of the first 21 and second 22 OR elements. Moreover, due to the fact that the outputs of the first 21 and second 22 OR elements, starting from the first group, are connected respectively to the second 4 and third 5 inputs of elements 2 of the memory of the lines of the associative drive, starting from the last line, masking is reoriented in this mode 1100145112

nth search argument from direct to mirror if the data orientation is in associative

the displayed form. the drive is not known.

Further, the description of this mode corresponds to the description of the previous mode. (56) USSR copyright certificate

Thus, the goal is achieved - 5 No. 760187, cl. G 11 C 15/00, 1978. The expansion of the expansion Kohonen T. Associative memories of the application of the device in the case of the device. M.: Mir, 1982, p. 169. p.3.9.

Claims (1)

The claims of the device, the second outputs of the elements of the ASSOCIATIVE MEMORY device of the associative drive column in the device, containing the associative matrix are combined and connected to the corresponding drive NN, where N is the memory capacity for the information input of the second register block of the polling register and max. , data, the first and second registers of fixation are information outputs of the first group, reactions of reactions, the first and second analyzers of which are 15 information matches of multiple coincidence, n rvy and moves the second group of devices Infor- second encoders, address decoder, mation outputs of the second group of the second address inputs of which are Location- register fixation reactions GOVERNMENTAL connected to inputs of the device for sampling the input data of which respective inputs second-. is the control input of the second analyzer of multiple matches of the address encoder, the information inputs of which and the controls of the polling register block and the inputs of the second encoder are combined masking data are inputs and are the second input of the mode reference. data of the device that controls the inputs of the device, the second state output of which is the control inputs 25 of which is the state output of the second block of polling registers and the mask analyzer of multiple coincidence data, outputs one through four, information the outputs of which from each group of outputs of which are connected to the corresponding fifth, fourth, information inputs of the second sixth and seventh inputs of the elements of the 30th unit, the outputs of which are addresses the corresponding column by the associative outputs of the second group of the device, the portable drive, the first outputs the first inputs of the memory elements of the line as the memory elements of each line of the associative drive are combined and the portable drive are combined and connected to the corresponding output are addressed to the corresponding 35 address decoder , the second inputs to the information input of the first register of memory copies of the 1st (where I 1N) line of reaction fixation, the control input of the associative drive are combined and the records of which the recording input input is connected to the first output of the 1st group of the second register of reaction fixation and the input of the outputs of the block of the polling and reading registers from the associative data storage drive, the second output of the 1st group is single and connected to the control of which is connected to the combined input devices, the informational inputs of the memory elements of the first strokes of the first group of which are the associative drive keys, distinguish the information outputs of the first group in that, in order to expand the first register register Actions, areas of application by providing formation outputs of the second group, the possibility of associative implementation is connected to the corresponding inputs of the first masked search data inputs of the first analyzer of the same search argument, multiple coincidence, the control input gg represented as in direct and in the grain and the control input of the first red-hot form without its re-encoder are combined and are the entries in the block of the polling registers and the output of the device mode Properties, masking the data, the inverter was entered and the first. The state output of which is the group of OR elements, the first and the status output of the first analyzer 55; the second outputs of each group of multiple-coincidence outputs, the information block of the polling registers and the masked outputs of which are connected to the corresponding data are connected to the first inputs by the corresponding information inputs, respectively, of the first and third, second and first encoders, the outputs of which of the fourth element OR correspond to the address outputs and the first corpse group, the second inputs of the third and fourth OR elements of all groups are combined and connected to the output of the inverter, the input of which is connected to the second inputs of the first and second elements of OR of all groups and is the control input of the device the outputs of the third and fourth elements OR of each group are connected respectively 57 with the fifth and fourth inputs of memory elements of the corresponding column of the associative drive, the outputs of the first and second OR elements, starting from the first group, are connected respectively to the second and third inputs of the memory elements of the rows of the associative drive, starting from the last line. QV3