SU680052A1 - Memory unit - Google Patents

Description

(54) STORAGE DEVICE

The invention relates to the field of digital computing and can be used in associative memory devices. One of the known associative memory devices based on conventional storage elements with an address sample consists of three arrays: an array storing inverse address information, a communication array, and the main array. In this device, the polling flag applied to the memory input is used as an address: to fetch a word from the first array that specifies the addresses of the communications array in which the cell address of the main storage device containing the word with the specified poll sign is written 1. Disadvantage The known device is its low speed. The closest technical solution to this invention is from a memory device containing an address memory block, whose inputs are connected to the outputs of the first and second address registers and the address bus, and the output to the input of the main memory block, the input of the first address register connected to the output of the free cell definition unit of the main memory, the input of which is connected to one of the outputs of the main memory cell occupancy register, the other outputs and inputs of which are connected respectively to the inputs and outputs of the memory block These signs of the main memory cells, information and output buses 2. The disadvantage of this device is the low speed, due to the fact that in the search mode addresses of the free zone are sequentially polled in the memory block of the adoBf- all cells of the table of the memory block zones . The purpose of this invention is to improve the speed of the storage device. The goal is achieved by the fact that the memory device contains a block for determining the free zones of the main memory, the register for the zones of the main memory and the element I, whose inputs are connected to the corresponding outputs of the register of the cells of the main memory, and the outputs are connected to the inputs of the register the occupation of the main memory zones, the outputs of which are connected to the inputs of the free zone determination module of the main memory, the outputs of which are connected to the inputs of the second address register and the inputs of the memory block of signs of occupancy of the main memory cells ovine memory.

The drawing shows a functional block diagram of a storage device.

The device contains an address memory block 1, a first address register 2, a second address register 3, a main memory block 4, a block 5 of the memory of signs of occupancy of the main memory cells, a block 6 for determining the free cell of the main memory, a block 7 for determining the free zone main memory, the register 8 of the main memory cells, the register 9 of the main memory zones, the element And 1 address bus 11, data 12 and output bus 13.

The memory device is robo the memory L indirectly addressing. The address for accessing the memory device corresponds to the cell in the address memory block 1, and the information is stored in the main memory block 4 in the cell corresponding to the address for block 1. The main memory block 4 is conventionally divided into zones. The number of zones is equal to the number of cells in the block of 5 memory. Attributes of employment. The zone of the main memory block consists of K cells, where K is the cell width of block 5. Each cell slot of block 5 characterizes the state of the corresponding cell of block 4. A single code corresponds to that cell.

The number of register bits of the main memory zones 9 is equal to the number of cells of block 5 and, accordingly, the number of main memory zones. Each bit of register 9 indicates whether there are free cells in the corresponding zones of the main memory block. The free zone of the main memory corresponds to the zero state of the corresponding register bit 9.

The free chip definition block of the main memory 6 generates the free cell address in the main memory zone, which is the first in the zone in the order of increasing addresses. o The storage device (memory) is as follows.

By initial reset, the device is reset (all registers are cleared and memory cells are cleared).

After the initial reset, the device enters the free cell search mode of the main memory block 4. The main memory free zone determination unit 7 analyzes the state of register 9 and generates the address of the free zone located first in the order of increasing addresses. The code of the zone address of the main memory block 4 is written to the second address register 3. The same address is used to read the contents of the cell from the memory block 5. The state 5 of each bit of the cell of the memory block 5 reflects the state of the memory cells of the corresponding zone of the main block. memory 4. Block 6 definition free cell main memory

0 analyzes the contents of the register 8 of the cells of the main memory, generates the address of the free cell, the first in the order of increasing addresses and puts it on the first address register of the register 2. After that, the corresponding register register 8 is transferred to the state And 10 repeats, imetots. Are there still free cells in this zone?

Q main memory. If all the bits are in the occupied state, the corresponding register bit 9 is transferred to the occupied zone. If the And 10 element determines the presence of free cells in this area of the main memory, the contents of the register 9 do not change. This is followed by a rewrite of the contents of register 8 into memory block 5 in the same cell from which it was read, at the address

0 formed by the block of determination of the free zone of the main memory 7.

As a result, the address of the free cell of the main memory 4, consisting of the main memory zone address recorded in the second address register 3 and the PSM address in this zone, recorded in the first address register 2, is obtained.

When the first treatment of external

0 devices to the storage device in the information recording mode this device is provided with the prepared address of the free cell of the main memory block 4. This address is entered into the corresponding cell of the memory block of address 1 and it records information from the input information buses 12 into the main memory block four.

When re-applying external

the device to the storage unit from the address memory block 1 is selected the address corresponding to the external storage unit 4 to the main storage unit 4 and depending on the operating mode of the storage unit, the information is recorded or recorded

input information buses 12 to the addressed cell of the main memory 4, or reading information from the addressed cell of block 4 to the output information buses 13.

Thus, the proposed device makes it possible to achieve a significant reduction in the search time for a free main memory cell due to the fact that

Claims (2)

analysis of the presence of a free zone and 1 location of a free cell (the address of the free cell of the main memory block). The invention contains a memory device containing an address memory block whose inputs are connected to the outputs of the first and second address registers and an address bus, and the output is connected to the input of a main memory block, the input of the first address register is connected to the output of a free cell determining block. memory whose input is connected to one of the outputs of the register of the main memory cells, the other outputs and inputs of which are connected respectively to the inputs and outputs of the memory block indicating that the main memory cells are busy, information mation and input buses, characterized in that in order to improve performance ust11 To 26 of the device, it contains a block for determining the free zones of the main memory, the register for the main memory zones and the element I, the inputs of which are connected to the corresponding outputs of the register of the cells of the main memory, and the outputs are connected to the inputs of the register of the zones the main memory, the outputs of which are connected to the inputs of the free zone determination unit of the main memory, the outputs of which are connected to the inputs of the second address register and the inputs of the memory block of indications of the cells of the main memory. Sources of information taken into account in the examination 1. Kaud. Bow, Jones D. D., Associative memory on conventional storage elements. Conference computer system and technologe, 1974, London, 1974, p. 195-20a 2. The author's testimony of the USSR 1 514287, cl. G 06 F 3/40/06/07/1976.