SU689439A1 - Device for interfacing main storage with processor and input-output channels - Google Patents

Description

on inputs - to the processor request lines and to the matrix of addresses from channels.

A disadvantage of the known device is the presence of a conflict in accessing the buffer memory between the requests of the processor and the I / O channels, which significantly reduces the speed of the device.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the device for interfacing an operational memory with a processor and input-output channels contains a buffer memory block whose address input is connected to the first output of the first processor address register, the register of recorded information, the first, second inputs and output of which are connected respectively, with the first, second inputs of the device and with the information input of the buffer memory block, the register of the read information, the first, second inputs and the first, second outputs of which are connected respectively to the third input of the device, the output of the buffer memory block, the first output of the device and the third input of the register of recorded information, the switch of the column address, the output of which is connected to the address input of the block of addresses, the switch of the address row, the output of which is connected to the input of the first register addresses of the processor and with the first input of the comparison circuit, the first priority block, the first, second inputs and the first output of which are connected respectively to the fourth, fifth inputs and to the second output of the device, and the second output is The first priority block is connected to the control inputs of the address switches of the row and the columns, the first code inputs of which are connected to the third output of the device, and the output of the address storage block are connected to the second input of the comparison circuit, a processor address switch, a channel address switch, an address register of the operational memory are entered e, the second processor address register, the second priority block, the trigger, and the OR element, and the device’s second input is the input to the second processor address register, the output of which is connected to the second codes The inputs of the row and column address switches, the first, second inputs and the first, second outputs of the memory address register are connected respectively to the output of the processor address switch, to the output of the channel address switch, to the third output of the device and to the information input of the address storage unit the inputs of the switches of the processor and channel addresses are connected respectively to the second output of the first register of the processor address and to the seventh input of the device, the fifth and eighth inputs

device OR is connected to the control input of the channel address switch and to the first input of the second priority block, the first output of which is the fourth output of the device, the second output of the second priority block connected to the control input of the processor address switch and one of the trigger inputs, the other which input and output

are connected respectively with the output of the comparison circuit and with the second input of the second priority block.

The block diagram of the device is shown in the drawing.

The device for interfacing the main memory with the processor and I / O channels contains a buffer memory block I, an address storage block 2, a second processor address register 3, a memory address register 4, a first priority block 5, a column address switch 6, a switch 7 addresses of the address, the comparison circuit 8, the first register 9 of the processor address, the register 10 of the read information,

trigger 11, second priority block 12, processor address switch 13, recorded information register 14, OR 15 element, channel address switch 16, fourth input 17, sixth input 18, fifth input

19, the eighth input 20, the seventh input 21, the second output 22 of the first priority block, the output 23 of the buffer memory block, the first output 24 of the device, the second output 25 of the first processor address register, the third

input 26 of the device, the third input 27 of the register of recorded information, information input 28 of the buffer memory block, the second output 29 of the second priority block, the second output 30 of the device, the fourth output 31 of the device, the second input 32 of the device, the first input 33 of the device, the third output 34 of the device , address input 35 of the buffer memory block, information input 36 of the address storage block.

The device works as follows.

When the processor accesses the memory, the op issues a request for the following 17 and the address for

input 18. When the I / O channels access the memory, they query the block 2 on input 19, the query on the main memory on input 20, and the address on input 21.

Unit 5 priority chooses the senior

the priority of simultaneously received requests and opens the column addresses and switch 7 addresses corresponding to the priority gates on the switch 6 and the row addresses. The highest priority in block 5 is the request

from the processor. The switch 6 of the column address connects the address input of block 2 to either the processor address register 3 or the RAM address register 4, depending on the output signal 22. Commutator 7 addresses p yes connects the address

; a number of main memory to the comparison circuit 8 and to the processor address register 9.

If, when the processor accesses input 26 to read information, the address of the row of the GENERAL memory is compared with one of the addresses written in the cell of block 2, the uniquely designated address of the column from the output of switch 6, this means that the required information is in block 1. the address of the corresponding cell of block 1 is written to register 9. At this address from block 1 to register 10 of the read information, the required information is selected from output 23 and transmitted to the processor via output 24.

If, when accessing the processor for reading information, the address of the row of the main memory is not compared with any of the addresses written in block 2, this means that the required information is not in block 1. At the output of the comparison circuit (addresses) 8 an incomparison signal is generated, which sets the trigger I to one state. From the output of trigger 11, the new request of the processor goes to the lower priority input of priority block 12. The highest priority in block 12 has a request arriving at input 20. In the absence of requests at input 20 at a given time, the processor receives a second request for priority in the RAM. The processor re-request priority signal from output 29 of block 12 opens switch 13 and allows reception of the address from output 25 of register 9 of processor address to register 4 of memory address. This address is used to access the RAM and read the information block. The read information arrives from the RAM to the input 10 of the read information register 10 and then sequentially through the input 27 of the register 14 and the input 28 of the block 1 is copied to the block 1 of the buffer memory. The address to which the information block will be recorded in block 1 is stored on register 9. The word required for the processor is extracted from the information block and the output 24 of the device is transferred to the processor from the output of register 10 of the read information. At the same time, the address of the row of the operational memory from which the information block is read is recorded at the input 36 into the cell of the block 2 defined by the address of the column. If a re-request priority is present and the memory block is free, the processor address to the main memory address received to register 4, the output 29 of priority block 12 generates a priority signal, which resets trigger 11.

It should be noted that I / O channels read information only from the main memory and write information only to the main memory. However, the information in block 1 of the buffer memory must be an exact copy of the information in the corresponding blocks of the main memory. Therefore, if a channel changes information in the main memory, you must either change (write) the information in block 1 of the buffer memory or cancel it in block 1 of the buffer memory, i.e. reset the presence of the information block corresponding to this address in block 2. In this device, the information is canceled by resetting the presence of the corresponding block of information in block 2.

When contacting the storage of information from the I / O channels to the device, two requests are received, which are set to one state at a time. The request for input 19 to block 2 is reset by the output signal 30 from the output of block 5. The request for input 20 to the main memory is reset by the signal from the output 31 of the priority of the channel request to the main memory while the memory block corresponding to this request is idle.

If at least one of the requests is present at input 19 or 20, the output of the OR 15 element generates a signal that opens the switch 16 and allows reception of the address from the I / O channels to register 4. The address from the I / O channels remains on register 4 until until the memory block corresponding to this address is started and until block 2 is cleared the presence of the information block corresponding to this address in block 1 of the buffer memory. Thus, the presence of priority blocks 5 and 12 and two address registers 3 and 4 makes it possible in parallel, (simultaneously) to process requests from I / O channels and the central processor. A conflict between these requests can occur only when the processor accesses the main memory, i.e., only when the trigger 11 is set to one. Since most of the calls (up to 95%) from the processor select data from the buffer memory block 1, the conflict between the channels and the processor to the main memory does not significantly affect the performance of the computer.

The device allows you to increase speed, approximately 25%.

Claims (3)

1. Author's certificate number 455345, cl. G 06 F 13/00, 1974. 2. The author's certificate number 495659, cl. G 06 F 3/04, 1975. 3.IENTENT UK No. cl. G 4 A, 1974 (prototype).