SU1228116A1 - Information retrieval device - Google Patents

Abstract

The invention relates to the field of computer technology and reduces the time spent searching for information in a memory unit by reducing the number of accesses to it to search for the required entry. The device contains upper and lower bounds address registers, respectively, adder, register, key, first and second comparison circuits, information register, memory block in which information is stored, output register, pulse generator, first to third OR elements, first and second groups of elements OR, reversible counter, pulse distributor, first and second elements I. Record search is initiated by the device start input. The key codes of the address of the upper and lower bounds are preliminarily supplied with the key codes of the desired record, the addresses of the last and first records in the dataset, respectively, and the input data are entered into the corresponding registers at the device installation input. 1 il. (L

Description

The invention relates to computing and can be used in database management systems.

The purpose of the invention is to increase the speed of the device by reducing the number of accesses to the memory unit to search for the required entry.

The drawing shows a block diagram of the device.

The device contains the upper limit address register 1, the lower limit address register 2, the adder 3, the register 4 keys, the first compare circuit 5, the information register 6, the memory block 7, the output register 8, the pulse generator 9, the first element OR 10, the first group of elements OR 11, the second and third elements OR 12 and 13 reversible counter 14, the distributor 15 pulses, the second comparison circuit 16, the first and second elements AND 17 and 18, the second group of elements OR 19, the device start input 20, the installation input 21 devices, input 22 of the device key code, input 23 addresses the top s device limits input 24 addresses the lower boundary of the device, the output device 25 address output 26 of the apparatus of feature.

Positions 27, 28 and 29 designate the outputs Equals, Less and More than the first circuit 5, respectively. The positions 30 to 33 denote the first, second, third, and fourth outputs of the distributor 15, respectively.

Each dataset record consists of a key and an information part. It is assumed that the data set records located in memory block 7 are sorted in ascending order of keys. It is required to find the address of the entry with the given key. The address of the cell (record) dividing the data set (or the remaining part of the data set, in which the search record is located) into two approximately equal parts, is called a boundary.

The device works as follows.

In the initial state, the counter 14 and the registers 6 and 8 are reset, the distributor 15 is set to the initial state. The inputs 22, 23, and 24 are supplied with the key codes of the search entry, the address of the last entry in the data set, and the address of the first entry in the data set, respectively. By impulse on

installation input 21 is allowed to write information to registers 4, 1 and 2, as a result of which the key code of the required record is entered into register 4, the address code of the last entry in the data set through the first group of elements OR 11 is written into register 1, and the address code of the first entry in the data set through the second group of elements OR 19 - into register 2. We will call the address of the last record in the data set the upper bound (BG), and the address of the first record - the lower bound (NG).

Record search is initiated by applying a pulse to the input 20, as a result of which the generator 9 is started. The pulses from its output through the distributor 15 are fed to various

device points. The first pulse appears at the output 30 of the distributor 15. This pulse permits the recording of information into the counter 14, as a result of which the sum of NG and VG from the outputs of the adder 3 with a shift of one bit in the direction of the lower bits is entered into the counter 14. This code is It is the first (in the following - the next frontier. Thus, the first frontier P, is determined as follows:

R / L (NG + VG) / 2J,

where lxd is the nearest integer less than or equal to x. After that, a pulse appears at the output 31 of the distributor 15, according to which the record is determined by the boundary, from the outputs of the memory block 7 is entered into the register 6. The first circuit 5 compares the key code of the desired record located in the register 4, with the code key entries read on register 6. In this case,

the following situations.

The code of the read entry matches the desired key code. In this case, the signal Equals at the output 27 of the first circuit 5, at which the address

the required record, located in the counter 14, is entered into the register 8, and the generator 9 stops.

The code of the read record is less than iso; My key code. In this case, the Smaller signal appears at the output 28 of the first circuit 5. This signal sets the summing mode of the counter .14 and opens the first AND 17 element.

31

The code of the read record is greater than the required key code. This leads to the appearance of the More signal at step 29 of the first circuit 5, according to which the mode of the counter 14 is set and the second element And 18 is opened.

According to the pulse at the output 32 of the distributor 15, the contents of the counter 14 are increased or decreased by one, depending on the given operating mode.

After that, a pulse appears at the output 33 of the distributor 15, which passes through either the first element 17 and the second element 18 and gates the recording of information either into register 2 or into register 1. As a result, one of the registers 1 or 2, the code generated in the counter 14 is recorded.

Thus, if the key code of the record read from block 7 is less than the required key code (i.e. there is no required record in the first half of the data set), then 1 adds 1 to the first line and the resulting code is written to register 2 as the lower limit A new set of data containing the required record, if the key code of the record read from block 7 is greater than the desired key code (i.e. in the second half of the data set of the required record is not present), one is subtracted from the first turn and the resulting code is written to register 1 in as the top face The new dataset containing the record you are looking for is Ü. Consequently, after sampling a first-line record and analyzing its key, the size of the data set is halved.

After that, a pulse appears again at the outlet 30 of the distributor 15, according to which the second boundary is formed according to the same rule

P, j L (Hr + 8r) / 2J,

only one of IG or 8G is not equal to the corresponding code when forming the first frontier.

In the future, the device operates as described.

If there is no record in the data set, then the moment will come when the SH will be less than NG (by one). This situation is fixed by the second comparison circuit 1–16, giving a signal at its output when

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the contents of register I are less than the contents of register 2. This signal will stop the generator 9 and pass to exit 26, which is indicated by the absence of a record with the desired key.

The search for the found record can be realized by setting the device to its original state and loading registers 1 and 2 of the address of this record, and register 4 its key. After that, a pulse is applied to the input 20, through which the required record will be read to register 6, and the pulse generator 9 will stop.

Due to the implementation in the proposed device of a different principle of forming a milestone, the number of records in the data set does not impose any restrictions. Therefore, to ensure the operation of the device, there is no need to artificially increase the number of entries. The actual number of records in this case coincides with the actual number of records. This leads to a more economical memory consumption and to a decrease in the number of accesses to the memory block to search for the required record.

Thus, the application of the invention allows to increase the speed of the device and reduce hardware costs.

Claims (1)

Invention Formula Device for searching information containing upper address address register, lower limit address register, adder, key register, first comparison circuit, information register, memory block, output register, first group of ISh elements, first OR element whose output is connected to blocking input pulse generator, the start input of which is the device start input, the outputs of the register of the upper boundary address are connected to the inputs of the first group of the adder, the information input of the key register is the input of the device key code, the inputs of the first and second groups of the first comparison circuit are connected to the outputs of the key register and the information register, respectively; the output is the same as the first comparison circuit connected to the first input of the first OR element and the gate input of the output register whose output is output the address of the device, and the address input of the memory unit are combined with the information input of the output register, characterized in that, in order to increase the speed of the device by reducing the number of accesses to the memory unit to search for the required entry, it contains the second, third OR elements, reversing counter, pulse distributor, second comparison circuit, first, second elements AND, and the second group of elements OR, with the inputs the address of the upper boundary of the device connected to the first inputs of the elements OR of the first group, the outputs which are connected to the information inputs of the upper boundary address register, the outputs of which are connected to the inputs of the first group of the second comparison circuit, the second group of inputs of which are connected to the second group of inputs of the adder and the outputs of the lower limit address register, the information inputs of which are connected to the outputs of the OR elements of the second group , the first inputs of which are connected to the inputs of the address of the lower boundary of the device, the output of the adder is connected to the information input of the reversible counter, the outputs of which are connected to the second inputs With the elements of the OR elements of the first and second groups, the installation input of the device is connected ten 15 20 five 0 With the first inputs of the second and third OR elements, the outputs of which are connected to the gate inputs of the upper boundary address register and lower limit address register, respectively, the output is less than the second comparison circuit connected to the output of the device characteristic and to the second input of the first OR element, the output of the pulse generator is connected to the impulse distributor's input, the first output of which is connected to the recording resolution input of the reversible counter, whose summation input is connected to the first input of the first element And and to the output Less than the first comparison circuit, the output of which is more connected to the subtracting input of the counter and to the first input of the second element AND whose output is connected to the second input of the second OR element, the second and third outputs of the pulse distributor are connected to the gate input of the information register and to the counting input of the reversing counter , the fourth output of the pulse distributor is connected to the second inputs of the second element AND and the first element AND, the output of which is connected to the second input of the third element OR, the setup input The device is connected to the gate input of the key register. yy VNIIPI Order 2288/50 Circulation 671 Subscription Random polygons pr-tie, Uzhgorod, st. Project, 4 Circulation 671 Subscription