SU1711185A1 - Device for information searching - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to simplify and increase the speed of the device through the implementation of the Iverson search method. The device contains upper and lower bounds registers, three AND elements, a memory unit, two comparison circuits, three counters, a key register, an output register, three groups of OR elements, four OR elements, a totalizer-subtractor, a search strategy register, two groups And elements, four delay elements, trigger with corresponding connections. The device is most effective when searching in small sets. 1 il.

Description

The invention relates to computing technology and can be used in hardware support systems for knowledge management systems (SUBZ).

The purpose of the invention is to simplify the device and increase the speed of the device by implementing a search in the data array ordered by the keys according to the Iverson method.

The Iverson algorithm is designed to find the argument K in the table of records Ri, R2, ..., R (M, arranged in order of increasing keys Ki K2 ... Km.

Initial installation I 1, U N.

Finding the middle. If U i, then

bad end of the algorithm, otherwise i n J

..

Comparison If K Ki, then go to 4. If K Ki, then go to 5. If K KI, then the successful end of the algorithm. If K 44, then the transition to 6. U.U 1-1 adjustment, the transition to 2,

Adjustment I.I i + 1, go to 2.

Initial installation i I.

Comparison If K Ki, then go to 9.

Increase i.i i + 1, go to 7.

Comparison If K Ki, then the successful end of the algorithm, otherwise the unsuccessful end of the algorithm.

The use of the device is justified when searching in small sets with a record number of 28-29. With N 210, the algorithmic complexity is reduced by only 11%.

The drawing shows a block diagram of the device.

The device contains an upper limit register 1, a lower limit register 2, a subtractor 3, a search strategy register 4, a subtracting counter 5, summing counters 6 and 7, a comparison circuit 8, a memory block 9, a key register 10, a comparison circuit 11, an output register 12. groups of 13-15 elements OR, groups of 16,17 elements AND, elements OR 18-21, elements 22-25 of delay, trigger 26, elements AND 27-29, start input 30, input 31 of the upper edge address (L

WITH

00

ate

tsy, input 32 addresses of the lower limit, input 33 of the code Criteria for changing the search strategy, input 34 of the key, output 35 of the address, output 36 of the sign of missing information. The elements 22-25 delay combined in the distributor 37 of the pulse.

The device begins to work on the search method by dividing in half.

When a trigger pulse is received from input 30, the upper limit address code from the input 31 through the elements of OR 13 is written to register 1, the lower limit address code from the input 32 through the elements

OR group 14, into register 4 of the criterion code for changing the search strategy coming from input 33, to register 10 of the key code of the desired record coming from input .34, and resetting trigger 26. At the time of recording, information from inputs 31 and 32 is removed. At the same time, the impulse is sent through the OR 21 and 22 elements, where it is delayed by the arrival time of the information in registers 1 and 2, and fed to the input 5b, and through the OR 20 element - to the input V of the adder-subtractor 3, allowing the arrival of the reduced and deductible. The difference is fed to the input of circuit 8, where it is compared with the number 44 coming from the output of register 4. Under the condition U -1 44, further operation of the device is similar. To the work of a known device. The impulse from the output of element 22 goes to element 23, where it is delayed by the time of the subtraction and comparison operations, to adder-subtractor 3 and circuit 8, respectively, to input SM and through element OR 20 to input V, permitting the flow of components to adder subtractor 1. Detained on item 24 for the duration of the operation of the summation in

calculator 4, the pulse permits writing the code from the output of adder-subtractor 3, shifted by one bit towards the low bit, into counters and 7 and into counter 6 through elements 16 of group 16 opened by a single potential from the inverse output of trigger 26, and the elements of group OR 15. Detained at element 25 at the time of recording information in the counters 5-7, the pulse arrives at the inputs C of the counters 5 and 7, carried out a decrease and an increase of their content per unit, respectively. The address from the output of counter 6 is fed to the address input of block 9, where it is used to sample records with a key that comes from the output of block 9 to circuit 11, where

compared with the key of the record sought, coming from the output of register 10.

The following situations are possible.

The key of the required record matches the key of the read record. The signal from the output Equal to circuit 11 permits writing the address of the required record from the output of counter 6 to the register

12, after which this address appears at exit 35.

The key of the required record is less than the key of the read record. The signal from the output of the Less circuit 11 is passed through the element OR

18 to the input V of the register 1, allowing the entry into it through the elements OR of the content group 13 from the output of the counter 5.

The key of the required record is greater than the key of the read record. Signal from the output More

circuit 11 passes through the element And 28, open unit, the potential from the inverse output of the trigger 26, and enters through the element OR 19 at the input V of the register 2, allowing writing to it through the elements OR

groups 14 of the contents of the counter 7. Also, the signal from the Outputs Less or More of the circuit 1.1 passes through the OR 21 element and is fed to a pulse distributor consisting of the elements 22-25. Provided

U - I 44 appears at the output signal Less than or equal to circuit 8, in which the trigger 26 is set to one. When this happens, the search strategy changes, and the device starts

work on a sequential search method.

When a signal arrives from the output of the element 24 to the input V of the counter 6, the contents of register 2 are written to it through

elements AND groups 17, opened by a single potential from the direct output of trigger 26, and elements OR of group 15.

When the scheme 11 in this mode, the following situations are possible.

The key of the read record is the same as

The key of the required record is similar to that described.

The key of the red record is larger than the key of the read record. Signal from the output More

circuit 11 passes through the element And 27, open unit potential from the direct output of the trigger 26 and is fed to the input of the counter 6, increasing its contents by one.

The key of the required entry is less than the key

read record The signal from the output of the Less circuit 11 passes through the element And 29, opened by a single potential from the direct output of the trigger 26, to the output 36, signaling the absence of information with the desired key. Formula invented

An information retrieval device containing an upper bound register, the information inputs of which are connected to the outputs of the OR elements of the first group, the first inputs of which are the addresses of the upper boundary of the device, the lower limit register, information inputs of which are connected to the outputs of the OR elements of the second group, the first inputs of which are the addresses of the lower boundary of the device, the control inputs of the registers of the upper and lower boundaries are connected to the outputs of the first and second elements OR, respectively, the first inputs to the second ones are connected to the information inputs of the adder, the second inputs of the OR elements of the first and second groups are connected to the outputs of the first and second counters, respectively, the information inputs of which are connected to the output of the adder, and the control inputs the record is combined, the memory block whose input is connected to the input of the output register, the output of which is the output of the device recording record, and the control input is connected to the output Equal to the first, the circuit Comparison, the first input of which is connected to the output of the register of the key, whose information input is the input of the device key, and the control input is connected to the start input of ycTpoucfea, the output Less than the first comparison circuit is connected to the first input of the first AND element and the second input of the first OR element. the trigger, the inverse output of which is connected to the first input of the second element AND, the output of which is connected to the second input of the second element OR, the third element AND, the fourth and fifth elements OR, the pulse distributor, the first and second corpses, the elements AND connected to the inputs of the elements of the third group, characterized in that, in order to simplify and improve speed, the adder is designed to be subtracted, and output, d of the adder-subtractor is connected to the information inputs of the first and second counters with a shift one bit in the direction of the lower bits, and the first counter is made subtractive, and the second comparison circuit is additionally entered into the device, the third counter and the search strategy register, whose information input is the input of the device search strategy, whose start input is connected to the control input the search strategy register, the output of which is connected to the first input of the second comparison circuit, the second input of which is connected to the output of the adder-subtractor, the addition control and subtraction inputs of which are connected to the first and second inputs of a third OR gate and the first and second output pulse distributor, third and fourth outputs of which are respectively connected to the write control input of the first counter and the clock with the combined first and second counters, the third counter output connected to an address input of the memory,

the output of which is connected to the second input of the first comparison circuit, the outputs of more and less of which are connected to the first and second inputs of the fourth OR element, the output of which is connected to the trigger input

pulse distributor, output More than the first comparison circuit is connected to the second inputs of the second and third elements And, the first input of the third element And is connected to the direct output of the trigger, the second input of the first element And, and the first inputs of the elements AND of the second group, the second inputs which are connected to the outputs the register of the lower limit, the outputs of the adder-subtractor are connected to the second input

the second comparison circuit, the second inputs of the elements And the first group, the second inputs of which are connected to the inverse output of the trigger, the installation input of which is connected to the output of the second comparison circuit,

The trigger reset input is connected to the device start input, the output of the absence of information attribute of which is connected to the output of the first element AND, the output of the third element AND is connected to the synchronous input of the third counter, the recording control input of which is connected to the third output of the pulse distributor, and the information inputs to the outputs of the elements OR the third group, the third entry of the fourth

element OR - with the device launch input.

i

Lsi i

J

Claims (1)

Formula of the invention A device for searching for information containing an upper boundary register, the information inputs of which are connected to the outputs of the OR elements of the first group, the first inputs of which are inputs of the address of the upper boundary of the device, a lower boundary register, the information inputs of which are connected to the outputs of the OR elements of the second group, whose first inputs are the inputs of the address of the lower boundary of the device, the control inputs of the registers of the upper and lower boundaries are connected to the outputs of the first and second elements OR, respectively, the first inputs of the cat They are combined and are the input to start the device, the outputs of the upper and lower bound registers are connected to the information inputs of the adder, the second inputs of the OR elements of the first and second groups are connected to the outputs of the first and second counters, respectively, the information inputs of which are connected to the output of the adder, and the recording control inputs are combined , a memory unit, the input of which is connected to the input of the output register, the output of which is the output of the desired device record, and the control input is connected to the output the first input of which is connected to the output of the key register, the information input of which is the input of the device key, and the control input is connected to the start input of the device, the output is Less than the first comparison circuit connected to the first input of the first AND element and the second input of the first OR element, trigger, inverse the output of which is connected to the first input of the second AND element, the output of which is connected to the second input of the second OR element, the third AND element, the fourth and fifth OR elements, the pulse distributor, the first and second element groups And entrances, the outputs of which are connected to the inputs of the elements of the OR of the third group, characterized in that, in order to simplify and improve performance, the adder is adapted to subtract, and the output of the adder-subtractor is connected to the information inputs of the first and second counters with a shift of one bit in side of the least significant bits, and the first counter is subtracted, moreover, the second comparison circuit, the third counter and the search strategy register, the information input of which is the input of the strategy, are additionally introduced into the device search device, the start input of which is connected to the control input of the search strategy register, the output of which is connected to the first input of the second comparison circuit, the second input of which is connected to the output of the adder-subtractor, the addition and subtraction control inputs of which are connected to the first and second inputs of the third OR element, and with the first and second outputs of the pulse distributor, the third and fourth outputs of which are connected respectively to the recording control input of the first counter and with the combined clock inputs of the first and second about counters, the output of the third counter is connected to the address input of the memory block, the output of which is connected to the second input of the first comparison circuit, the outputs of More and Less of which are connected to the first and second inputs of the fourth OR element, the output of which is connected to the start input of the pulse distributor, the output is Greater than the first the comparison circuit is connected to the second inputs of the second and third elements AND, the first input of the third element And is connected to the direct output of the trigger, the second input of the first element And and the first inputs of the elements AND of the second group, the second inputs of which are connected to the outputs of the lower boundary register, the outputs of the adder-subtractor are connected to the second input of the second comparison circuit, the second inputs of the elements of the first group., the second inputs of which are connected to the inverse output of the trigger, the installation input of which is connected to the output of the second comparison circuit, the input the trigger reset is connected to the start input of the device, the output of the lack of information indicator of which is connected to the output of the first element And, the output of the third element And is connected to the clock input of the third counter, the input of the recording of which is connected to the third output of the pulse distributor, and the information inputs to the outputs of the OR elements of the third group, the third input of the fourth OR element to the start input of the device.