SU1386988A1 - Device for determining extremes - Google Patents

Abstract

The invention relates to automation and computing and can be used in information processing devices designed to search for local and absolute extremes of a function. represented by an array. The aim of the invention is to increase the speed of the device by sequential pipeline comparison. The device contains synchronous registers 1-6, of which four (1-4) with dynamic control, two circuits 7 and 8 comparisons, counter 9, three D-flip-flops 10-12, two elements And 13 and 14, five elements 15-19 delay. The device allows the sequential passage of array numbers representing a function through the device to search for the absolute maximum or minimum with its address, as well as determine the corresponding local extrema with their addresses, the output of which is synchronized depending on the specified mode 2 or . with

Description

(L

with

SA 00 O5

:about

00

oo

I The invention relates to automation and computing and can be used in specialized information processing devices designed to search for local and absolute extrema of a function represented by an array.

The purpose of the invention is to increase the speed of the device by sequential pipeline comparison. ; FIG. 1 shows a functional device; in fig. 2 - temporary diagrams of the device operation.

The device contains registers 1-4 with dynamic control, registers 5 and 6, 7 and 8 comparisons, counter 9, D-triggers 10-12, elements I 13 and 14, delay elements 15-19, information inputs 2D, input 21 device synchronization, mode selection input 22, outputs 23 local extremes, output 24 gating local extremes, outputs 25 absolute extremes, outputs 26 addresses of the absolute extremum and outputs 27 addresses of the local extremum.

 The device works as follows.

Before starting operation, registers 1-6, counter 9, and triggers 10-12 are set to the zero state. To the input mode selection sends the signal "Log. 1 when searching for a maximum or a signal “Log.O when searching for a minimum.

Moreover, in the presence of logic "1, single signals are generated at the control outputs of the circuits 7 and 8 of comparison, if h (number, respectively, on the first and second yodes (outputs of registers 1 and 3) are less than h; isl, respectively, on the second and first inputs (outputs of registers 2 and 4).

If there is a logical "O" on the control outputs of the comparison circuits 7 and 8, single signals are generated if the number on the first and second inputs, respectively, is greater than the number on the second and first inputs, respectively.

Consider the operation of the device on the example of the search for the absolute maxi.mum.

On the first clock pulse (Fig. 2a), the following period is At tcpH-tT2 + - -tH-t-tp2, where tcp is the comparison time of the numbers by the comparison circuit; tra is the trigger trigger time, in is the delay time of the AND element; tp2 is the response time of the register arriving at the synchronization input of device 21, the first number arriving at input 20 is entered into register 1.

In the next clock cycle for the first clock pulse delayed by the delay unit 15 per clock (Fig. 2b), the delay time of which, the first number is entered into register 2, and the second number over the second clock pulse (Fig. 2a) - into register 1. The second and the first numbers are compared using comparison circuit 7, with the output of the circuit

0

five

0

five

y

 H

0

five

0

five

We compare a single signal if the number in register 1 is less than the number in register 2. The result of the comparison is entered in the next clock cycle into trigger 10 according to the first clock pulse delayed by the clock delay element 16 (Fig. 2c), the delay time of which. The result of the comparison is shown in FIG. 2d All signals whose values depend on the ratio of the numbers being compared are shown in dashed lines. Using the same clock pulse (Fig. 2c), the first number is entered into register 3, one is added to the contents of counter 9, and the zero value of counter 9 is written to register 5. If the second number is less than the first, then the first number is a local maximum. In this case, the pulse delayed by 19 delay elements for the time required for recording in trigger 10 and register 3 passes through AND 13, the other inputs of which contain logical signals "1 from the direct output of trigger 10 and inverse output of trigger 1, on the output 24 synchronization of local extrema. This signal (Fig. 2g) from register 3, at output 23, finds the value of the local maximum, and at output 27 from register 5, the address of the local maximum.

In the next clock cycle on the first clock pulse delayed by delay element 17 (fig. 2d), the delay time ti7 ti6-14, the result of comparing the first and second numbers is rewritten from trigger 10 to trigger P. This same clock pulse passes through element 14, to the second input which receives permission from the inverse output of the trigger 12, and rewrites the first number from register 3 to register 4 and its address from register 5 to register 6.

In the same clock cycle, the second sync pulse (Fig. 2c) records the trigger 10 for comparing the second and third numbers, writes the second number to register 3, the second number is entered into register 5, counter 9 is added to register 5, and one is added to counter 9.

If the second number is greater than the first n of the third numbers, it is a local maximum, and at the inputs of the triggers 10 and 11 there will be logical "1s that allow the passage of a pulse from the output of delay element 19 through element 13 to gate 24 of local extremes (FIG. 2g). This signal from register 3 reads the second number on output 23 and its address on output 27.

The second number in register 3 is compared with the first number in register 4 using the comparison circuit 8, and the result of the comparison of numbers (Fig. 2i) is synchronized with the delayed delay element 18, whose delay time (Fig. 2h) is written to the trigger 12.

If the number in register 3 is greater than or equal to the number in register 4, then the output of the comparison circuit 8 will be a logical "O, which is written to flip-flop 12. Logic" 1 from the inverse of flip-flop 12 allows the clock from the output of delay element 17 to pass through an AND 14 register syncs 4 and 6, and the number from register 3 is rewritten to register 4, and its address is from register 5 to register 6.

Further operation of the device is similar.

According to the last (nth) clock pulse (Fig. 2a), the last number is written to register 1 and compared with the help of the circuit.

Comparison with the (n-1) -th number recorded in register 2 according to the (n-1) th pulse (Fig. 26).

In the next cycle, the result of the comparison by the (p-1) -th pulse (Fig. 2c) is entered into trigger 10, and the value of (p-1) -th number - into register 3, the result of the comparison between (p-1) -th and -2) -th numbers are rewritten from trigger 10 to trigger 11. If the (n-1) -th number is more than the n-th and (n-2) -th numbers, it is a local maximum, and the signals from the outputs of the trigger 10 and 11 ra decides the passage of the (n-1) th pulse from the output of the delay element 19 through the element

13 to output 24 synchronization of local extremes (FIG. 2 g).

In the next clock cycle, the value of the (n − 1) th number recorded in register 3 is compared using comparison circuit 8 with the contents of register 4, in which the current absolute maximum is stored. If the (n-1) -th number is greater than or equal to the number in register 4, the TC at the output of the comparison circuit 8 will be a logical "0, which is written to the trigger 12 according to the signal from the output of the delay element 18 (Fig. 2h), and the logical" 1 from the output of the trigger 12 permits the passage of a pulse from the output of the delay element 17 (Fig. 2d) through the element And

14 on the inputs of the record registers 4 and b (Fig. 2k). From register 3 (n-1) -th number is rewritten to register 4, and its address is from register 5 to register 6. In the last cycle, the n-th number is compared in the same way, and as a result of processing, the absolute maximum is selected in register 4, and register 6 is its address.

Claims (1)

Invention Formula A device for determining extrema containing the first to sixth registers, the first and second comparison circuits, the counter, the first and second element I, and the information inputs of the device are connected to the information inputs of the first register, the bit outputs of which are connected to the first group of information inputs of the first comparison circuit and with the information inputs of the second register. the outputs of the bits of which are connected to the second group of information inputs of the first comparison circuit and with the information inputs of the third register, the output of the bits of which are the first outputs of the device extremum and connected to the information inputs of the fourth register, the outputs of the bits of which are connected to the first group of information inputs of the second, , a swarm of the comparison circuit, the control inputs of the comparison circuit are connected to the input of the device mode selection, the output of the gating of the local extrema of which is connected to the output of the first AND gate, the outputs of the counter bits are connected to data rows 5 inputs of the fifth register, the outputs of which bits are the output of the device extremum address, characterized in that, in order to improve speed, the first, second, third and fourth registers in it are executed with dynamic control and five delay elements are entered into it and three D-flip-flops, the device synchronization input is connected to the synchronization input of the first register with dynamic control and the input of the first 5 delay elements, the output of which is connected to the synchronization input of the second register with dynamic control and with the input of the second delay element, the output of which is connected to the synchronization inputs of the first D-flip-flop, the third register with dynamic control and the fifth register, with the counting input of the counter and c the inputs of the third and fourth e. 1 delays, the output of the third delay element is connected to the synchronization input of the second D-flip-flop, with the first input of the second element I and with the input of the fifth delay element, the output of which is connected to the synchronization input of the third D-flip-flop, D-input of which is connected to the output the second comparison circuit, the second group of information inputs of which is connected to the outputs of the bits of the third register. with dynamic control, the output of the first comparison circuit is connected to the D input of the first D-flip-flop, the direct output of which is connected to the first input th first AND and 5 D-input of the second D-flip-flop, the inverse output of which is connected to the second input of the first element And, the third input of which is connected to the output of the fourth delay element, the inverse output of the third D-flip-flop connected to the second input of the second element And, the output of which is connected to the inputs synchronization of the fourth register with dynamic control and the sixth register; the outputs of the bits of the fourth register with dynamic control are the outputs of the absolute extremum of the device; the outputs of the bits of the sixth register are outputs rez absolute extremum device. five Fi.g