SU1259264A1 - Device for loading files - Google Patents

Abstract

The invention relates to computing and can be used in computing systems for communicating processors with external and storage devices, as well as in automated data banks. The purpose of the invention is to increase speed. The device contains a group of input registers, a register of the file tag, a group of comparison circuits, two groups of AND blocks and a group of output registers. New in the device is the use of a pulse generator, counter, decoder, control trigger, element OR NOT, two elements AND, element group OR, two groups of elements AND, two groups of prohibition elements, three delay elements, the third group of blocks of elements AND, the OR element and their relationships, thereby achieving the object of the invention. 1 il.

Description

The invention relates to computing and can be used in computer systems for communicating processors with external storage devices, as well as s in automated data banks. The aim of the invention is to increase speed.

The drawing shows a block diagram of the proposed device. ABOUT

The device contains a group of input registers 1, a group of inputs 2 devices, a group of elements AND 3, a block of elements OR 4, a first group of prohibition elements 5, a third group of 15 blocks of elements AND 6, a block of 7 elements and, the first delay element 8, a register 9 of the sign file, the element OR-NOT 10, the second element 1G delay, the group of comparison schemes 12, the second 20 group of prohibition elements 13, the second group of blocks of elements AND 14j the first group of blocks of elements AND 15, the group of output registers 16, the group output. Device IDs 17, third delay element 25 18, device file tag 19 output, element WEE 20, pulse generator 21, first element E 22, decoder 23, counter 24, second element 25, control trigger 26, 30 device start input 27 , the first control output 28 of the device, the output 29 of the file format of the device and the second control to the output 30 of the device .35

The initial state of the device is characterized by the fact that control trigger 26 is set to O ..

On inputs 2 to registers 1, it supplies 40 seconds to an array of operands (records) with attribute parts, and the attribute parts can be different or the same. The number of identical records (files) may be different. 45

Since registers 1 received an array of file records, the codes of the file attributes are not equal to zero at all its second outputs, therefore 50 single signals are formed at all outputs of the OR 4 elements.

. Through the prohibition elements 5 connected to the outputs of the elements OR 4 according to the priority scheme, all the elements 55 and 6 are blocked, starting with the second. Elements 6 and 6 are open, so simultaneously with the installation of counter 24 in O, a start signal from device input 27 causes the file attribute from the first input register 1 to be transferred to register 9.

The signals from the outputs of register 9 are fed to the first inputs of all comparison circuits I2, the second inputs of which are supplied with the file attribute codes from the corresponding input registers 1. At the outputs of the comparison circuits, where the codes match, the single signals are generated. Let the codes coincide in circuits 12 and 12. At the same time, at the output of the element OR 20, a single signal is formed, which opens at the second input element AND 22. At the same time, a single signal from the output of the comparison circuit 12 along the inverse inputs closes all prohibition elements 13. A single signal from the output of the comparison circuit 12 is open on the second input of the element And 3 and on the second inputs of the elements of the 14.

After some time delay, determined by delay element 8, is set to 1 trigger 26. The delay element, by element 8, selects based on the transient process time, in block 7 And elements, re-2 histor 9, comparison circuits 12 and the element OR 20 .;

Since the element AND 2 2 is open, the first impulse of the mash 21 gene enters the counting input of the counter 24, in which the content becomes equal to one. At the same time, at the first output of the decoder 23, a single signal is formed, through which elements AND 15 are opened, and the contents of register 1 (record of file J only) are transferred to register I6. After some time delay, determined by the delay element 18, is set to O register 1 through the open element And 3. The delay element 18 is necessary to coordinate the time of transients in the device when transmitting a selection of: A small file to the output register 16.

After installation in register I, the signal from the output of the comparison circuit 12 is removed, which prevents all elements 13 from being opened via the first BtiM inverse inputs. At the same time, a single signal is removed from the output of the element OR 1, and the prohibition elements 5 are removed by the first inverse inputs.

Since a single signal is present only at the output of the comparison circuit 12, the single signal from the output of the element OR 20 and the element 25 is closed at the inverse of the input, and, besides, the element C 3 is open, and at its output a single signal is opened from the element 14, .

The next pulse of the generator 2, the contents of the counter 24 becomes equal to two, and at the second output of the decoder 23 a single signal is formed, according to which the file record from register 1 is transferred to register 16.2 through AND 15, After some time is set to O register 1.

Since after installation in O register 1, the output signals of all comparison circuits 12 become equal to zero, the element 25 is turned off at the inverse input by a zero signal from the output of the element OR 20, and the delayed pulse of the generator 21 from the counting input of the counter 24 element 11, the delay is set to O flip-flop 26. The delay time of element 11 is determined by the transient time in AND 3 elements — register 1, comparison circuits 12, and OR element 20.

After setting in About trigger 2, the output of counter 24 is fixed to the file format, i.e. The number of output registers is 16 (in the considered example, the file format is two) in which the file records are located.

The signal at the output 28 of the computer loads the selected file records from the outputs 17, then input 27 sends the next start signal by which the device selects the first non-zero file attribute, and after recording it in register 9 it works in the same way as described.

Upon completion of the review of all file files, the registers 1 are in the zero state, therefore, at the output of the OR-NOT 10 element, a single signal is generated that arrives at output 30 and indicates that the device is ready to receive the next array of file records.

In the future, the device works similarly.

Claims (1)

Invention Formula A device for loading files containing a group of input registers whose inputs are a group of information inputs of the device, a file flag register, a group of comparison circuits, first and second groups of AND blocks, a group of output registers whose outputs are device information outputs and the register output is file connected to the first inputs of the group matching circuits, the second inputs of which are connected to the direct outputs of the corresponding input registers of the group, the inverse outputs of which are connected to the first input of the corresponding blocks of elements AND of the second group, the second input of elements AND of the first block of elements AND the second group are connected to the output of the first comparison circuit of the group, the outputs of the blocks of elements AND of the second group are combined and connected to the first inputs of the blocks of elements AND of the first group whose outputs are connected with information the inputs of the corresponding output registers of the group, characterized in that, in order to increase speed, a pulse generator, a counter, a decoder, a control trigger, whose zero output is with the output of the sign of the device, the element OR NOT, two elements AND, a group of elements OR, a group of elements AND, a block of elements AND, two groups of prohibition elements, three delay elements, a third group of blocks of elements AND and the element OR, the output of the pulse generator is connected to the first input of the first element I, the second input of which is connected to the inverse input of the second element I and to the output of the IC element, the third input of the first element I connected to the single output of the control trigger, and the output to the input of the first delay element and to the counting the input of the counter, the outputs of which are the outputs of the device file format and connected to the inputs of the decoder, the outputs of which are connected to the second inputs of the corresponding blocks of the AND elements of the first group, the output of the first delay element is connected to the input of the second delay element and the first inputs of the AND elements S the groups whose outputs are connected to the installation inputs in O of the respective input registers of the group, the direct outputs of which are connected to the inputs of the corresponding elements OR of the group and to the first inputs of the corresponding blocks of elements AND of the third group, the outputs of the elements OR of the group are connected to the corresponding inputs of the element OR NOT the output of which is the output of the indication of the presence of information of the device, the output of the second delay element is connected to the direct input of the second element AND, the output of which is connected to the zero input of the trigger control neither the output of the first element OR of the group is connected to the second input of the first block of elements AND of the third group, the direct input of the i-th element of the prohibition of the first group (where i 1,2, ..., h-1; h is the number of input registers of the group connected with the output of the (i + l) -ro element OR of the group, the J-and inverse input of the i-th element of the prohibition of the first group (where J 1,2, ..., I) is connected to the output of the .1-th element of the OR group, the output The 1st element 3arfpeTa of the first group is connected to the second input of the (t + l) -th block of elements AND of the third group, the outputs of all the blocks of elements are 562646 The third group is connected via OR to the first input of the AND block, the output of which is connected to the register information input from the file sign, the outputs of the group comparison circuits are connected to the corresponding inputs of the OR element, the direct input of the 1st prohibition element of the second group is connected to the output (+1) -and 10 circuits of the group, the j-th and inverse input of the i-th element of the prohibition of the second group is connected to the output of the j-th group comparison scheme, the i-th element of the i-th element of the prohibition of the second group of SoS is dinene with the second input of the (i + 1) -th block elements of the second group, the output of the first group comparison circuit is connected to the second input of the first element AND of the first group, the output of the i -th 20 elements of the prohibition of the second group It is not with the second input (i + l) -ro of the block of elements of the second group and with the second input of the (1 + 1) -th element of the group, the start input of the device connected to the input of the installation in the counter Oh, with the second input of the block of elements AND through the third delay element with a single control trigger input, the output of the file tag register 30 is the output of the device file tag. P   R L "SI Cm ha Editor O. Yurkovetska Order 5123/47 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Compiled by, Gudovsky Tehred I. Popovich Proofreader E. Roshko