GB1445663A - Data processing system - Google Patents

Abstract

1445663 Data processing INTERNATIONAL BUSINESS MACHINES CORP 12 Aug 1974 [17 Sept 1973] 35370/74 Heading G4A A data processing system including registers (16-20, Fig. 1, not shown) connected by a bidirectional data path (22) to a processing unit (11) includes gating 65-68 (Fig. 2a) for selecting a register module for reading into from the data path during a first part of an operating instruction and gating 71-74 for selecting a register module for read out to the data path during a second part of an instruction. As described gating (76-79, Fig. 2b, not shown) is also provided to reset the selected register module during the first part of the instruction. Read out from a further register may be effected during a third part of the instruction. Each of four modules includes four storage locations one of which 52 is shown in Fig. 2a. Data is read in from for example line 63 (forming part of the bus (22)) to the "0" bit latch 53 of the selected module (determined by the signals on lines 49, 50) when a signal clock 0 is negative, a further signal (clock 1) resetting the latches. Data stored in the latch is read out when its associated module is selected (so that AND gate 55 is primed) and when clock 0 is positive (so that AND gates 86 are primed, there being eight such gates) so that an eight bit word is fed to the bus (22).