DE2440479A1 - PROCESSOR WITH A SWITCHING DEVICE FOR A BIDIRECTIONAL DATA LINE - Google Patents

Description

Boeblingen, August 15, 1974 j o-f e

Aniaelderin: International Business Machines

Corporation, Armonk, W.Y. 10504

Official file number: new registration Applicant's file number: IiO 973 015

Processor with a switching device for an oidirectional

Data line _____________

The invention relates to a processor with a switchover device for a bidirectional data line according to the preamble of claim 1,

The introduction of integration techniques with a high component density led to a change in the processor architecture of the data processing systems in order to take advantage of these technologies to be able to take over and to keep effects that limit the application of these technologies to a minimum. Since this is a practical There is a limit to the quantity of circuit functions that can be performed with a single module it is necessary to distribute the system functions to a number of such modules. It is essential here the division of functions so that the number of communication lines between the modules is kept as low as possible, which can be achieved that the functions in the modules can be combined into groups. As the number of interconnection lines is limited to a circuit module, additional methods must be sought to increase the number of connections if the function of a module is not to be restricted depending on the available connections.

The architecture of the processor in which the invention is implemented is, has a common bidirectional data line to connect the system components, which facilitate the transmission of data in

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within the system on a single data path, whereby only one set of connections on each module is required for both sending and receiving data.

In US Pat. No. 3,384,877, a register is switched through various devices described, but not via the multiple switching stages of a bidirectional data path disposes. The technique given here therefore has the disadvantage that it cannot be used for the connection of highly integrated circuit modules with a very high component density.

It is therefore the object of the present invention to provide an economical one Specify a solution for the connection of circuit modules on which the components are integrated with a very high Density are applied.

This problem is solved by those specified in the main claim Characteristics,

Further advantageous configurations, developments and features can be found in the subclaims.

In this way, the invention achieves the advantage that in electronic data processing systems, which are made up of integrated Circuit modules with a high component density are constructed, savings in input / output connections are achieved and a reduction the complexity of the wiring of the modules with one another is made possible without the processing speed at the same time the system is reduced.

In the following an embodiment of the invention is based on the Explained in the accompanying drawings. Show it:

1 shows a schematic representation of the architecture

of the processor in which the present invention is used, the data line and the functional units associated with it

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are shown,

Figs. 2a, 2b, arranged according to FIG. 2, a cross section through

the logic circuit diagram of a register module with the selection circuits and corresponding memory and switching positions connected to the bidirectional data line, and

Fig. 3 is a timing diagram showing the division of an In

instruction cycle and the clock pulses, which the connection between the register module and the bidirectional data line.

1 shows a schematic representation of a processor, which via an arithmetic and logic unit CALU) 11, a control section with modules 12, 13 and 14 as well as five registers 16, 17, 18, 19 and 20, which are all connected via a common bidirectional data line 22, has. In the case of the example assumed environment, the bidirectional data line (data path) 22 is 8 bits wide.

The control section has a command address module 12 in which an address is generated and via the data path 24 to the module 13 is transferred, the latter of which is a read control memory according to its structure (ROS) 13 is. Depending on the address on the data path 24, the ROS module 13 transmits a 16 bit wide instruction via the data path 25 to the instruction decoding module 14, Using the control line 26, the 16-bit wide instruction from data path 25 using the AND gate 27 is switched through to register (ISP) 28, in which the instruction is stored in a series of 16 interlocking circuits will. 8 bits can be switched through from the register 28 to the bidirectional data path 22 with the aid of the AND gate 30, if this is specified in the control section of the instruction.

An address RO 973 015 509812/0990 transmitted to the ROS module 13 via the data path 24

-Ilse is 14 bits wide and consists of 8 low-part bits, those from the instruction address register (IAR) 22 and from 6 high-order bits that are from one of the page registers (PO) 33 or (Pl) 34 can be delivered. The page register for a particular instruction is selected with the aid of a latch circuit 36 which supplies an output signal which, because of the inverter 37 and the AND gates e 38 and 3y, is always one of the two side registers on the data path 24 switches through.

The arithmetic and logic unit 11 consists of an A register 41 and a B register 42, which are connected to the bidirectional data path 22 via the AND gates 43 and 44, respectively. The result of an arithmetic and logical operation becomes Transferred to the common data path 22 via the UiMD gate 45.

FIG. 2 shows a cross section for a circuit with 4 typical register modules which use a NOR logic and in the architecture according to Fig. 1 are included. The selection logic, one of 32 binary data storage positions 52 and one of 8 exit gate positions are shown 84. Four 8-bit wide registers are also shown, which are used by the input signals on lines 47 and 48 can be selected.

Each of the 32 data positions in the four 8-bit registers contains a latch circuit 53 (Fig, 2a) and AND gate blocks 54 and 55j as shown at 52 for the register O / BitO data position The data is input via line 57 if the register has been selected from input signals showing a negative Signal level (negative signal) on the line .. {. 59 cause which switches the AND gate 54 through. If, on the other hand, a positive signal is received on line 60, then the condition is for the AND gate 54 is not met, so that on line 57 a negative output signal that sets the latch circuit 53 so that a logical one at this data position can be sensed via line 61. When on the line 60 a negative signal is received, then the condition for the AND gate 54 is met, so that a positive

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ves output signal occurs, which sets the locking circuit 53 so that a logical rJull can then be sensed via the line 61 at the data position mentioned. This corresponds to the lack of data. The common bidirectional data path 22 has 8 parallel lines in the selected exemplary embodiment. Line of these lines, which takes over the signal exchange with the register shown in FIG. 2, is line 63 ₃ which exchanges signals with the bit 0 position of all four module registers. If a negative value is sensed on line 63 then it is indicative of data. If, on the other hand, the value is positive, then this means that a data bit is missing.

The switching of input data to the bit positions of a selected register is carried out with the aid of the AND gate block 65, 66, 67 and 68, which switch through registers 0 to 3, respectively. Each of these IMD gates mentioned has an input line 69 which makes a selection of the register module when there is a negative signal HOD SLCT. A second input line 71) carries a negative clock signal -CLK -O, which is a clock signal for limiting the switching of the gate to a desired section of the cycle. The last two Lines e.g. 47,48 of each AND gate block e.g. 68 are register select lines., which respond to input signals of the register selection AND blocks 71 to 74. Although the output of each Line, for example line 75, could be used by the inverter 76, but so there are two logical delays eliminated by using the same input signals used by the register select AND block 71 to 7 ^. If all input lines of one of the AND gate blocks 65 to are negative, then a positive signal appears at the output, which is inverted and transmitted to each of the 8 AND gates that correspond to the AND gate 54 on the 8 binary memory locations, assigned to the selected register.

another row of 4 AND gate blocks 76, 77, 78 and 79 (Fig. 2b) serve to output a reset signal via line 82 to the

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2U0479

Interlock circuits e.g. 53 of a selected register. Each the UiNiu gates 76 to 79 have the module selection line as the input line 69 and a pair of clock control lines 70, 80, the transmit the clock signals labeled -GLK U and -ULK 1. the the last two lines then select the register. These lines are also the same true and complementary üinput cable combinations that are used to select the appropriate. Register ü to 3 are used, as they are also used for the register selection and for the selection of the gate-on control signals for the transmission of the data to the appropriate interlocking circuits be used. If each of the five input lines of one of the iMD gates 7b to 79 produces a negative signal, then appears at the output a positive signal which is transmitted as an input signal to the AND gate block, which is connected to the AND gate 81 in corresponds to the interlock circuit 53, namely in the 8 interlock circuits, which are assigned to the specified register, as shown for register ü / bit 0 of data position 52, where the lines 49, 50, 69, 70 and 8ü carry negative signals, the UWD gate 76 is actuated and a positive signal on the line 82 transmits to the UiJD gate 81 which is the locking circuit 53 resets again. At the same time, the positive (reset) signal on line 82 also goes to each of the other 7 Bit positions of register 0 transferred to all 8 latches which has register 0 in this module.

A row of 8 output gates switches the data of the four registers of a module to the data path. One of the 8 positions is shown in Fig. 2a, namely position 84, the data from the U bit position switches each of the four registers in the module to the common bidirectional data path 22. The (through) AND gate block 86 for bit 0 receives the signal of the O-bit position of each of the four registers 0 to as input signal 3 via lines 88, 89, 90 and 9I, respectively. The remaining entrances are the module select line 69, the (-CLK 0-) line 70 and (-CLK l-) line 80, the latter two lines being clock lines. Since the input connected to line 70

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is, an inverter 9 2 is connected upstream, this line only carries the correct input signal if this is positive. If the The module selection line and the clock lines carry negative signals, then the data of the selected register bit positions i.e. in the corresponding interlock circuit e.g. stored value, transmitted to the data path line 63, Since the Register select input to the AND gate block, which is the AND gate 55 corresponds to the bit positions of the unselected register, is positive and its output is negative, each of the three lines to AND gate 86 from unselected register data bit positions a negative signal, so that this gate is turned on and the output of the AND gate 86 of the input is controlled by the selected bit position. When register O is selected and line 61 is positive Signal leads, what a negative output signal of the AND gate 55 is indicative, then the AND gate 86 is switched through. The output of this AND gate 86 on line 93 is positive, is transmitted inverted on the line 63 in order to indicate the presence of a data bit for this bit position. if there is a negative value on the line 6l, which indicates the lack of it of data is indicative, the AND gate 55 is switched through, which in turn emits a positive output signal on the line 88, so that the AND gate 86 is not switched through and a negative output signal is output on the line 93, which is now is inverted to deliver a positive signal to the data path line 73, which in turn accounts for the lack of data on the sensed bit position z, B, of the latch circuit shown in Fig. 2a 53 is indicative.

The selection of one of the four registers O to 3 of the register module 2a, b is effected by signals on the two lines 47 and 48. The signals on the two named lines 47 and 48 and the inverted or complementary values on the lines 49 and 50 are used in a standard two-bit decoder Decoüiert that uses the AND gate blocks 71, 72, 73 and 74 to

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to allow selection of one of four registers in the module for each of the four possible combinations on input line 47,48. If both input signals at one of the AND gate blocks 71 'to 74 are negative, then the UiiD condition is met and a positive signal appears at the output. The signal on each of the output lines 94, 95, 36 and 97 is inverted by an inverter 76 to produce a negative select signal for the AND gate block associated with the UiiD gate 55 in each of the 8 selected register bit positions.

Fig. 3 shows that an instruction cycle of the processor in three Sections labeled R, B, and A are divided. • Each of the sections can, as indicated in the figure, can be divided into four parts. During the R time, the data is grounded on the common bidirectional data path 22 (.Fig, 1) from the output of the arithmetic and logic unit 11 in a selected register. During the period in which the Clock O is negative (-CLKO), data from the data path 22 (in 2a represented by the line 63) are transferred into the binary memory positions of the selected register. While of the first third of the gate on cycle segment are the stored values in the memory positions of the selected register not necessarily correct, as an earlier value is still in the relevant memory location and the setting of the new value can prevent. During the second third of the Gate On cycle segment the 8 bit positions of the selected register are reset with the result that if clock 1 is at the end of the Reset becomes positive (+ CLK 1), the value set at the register data positions is now the correct new value. While the B time, the content of a selected register via the gate 86 and the bidirectional data path 22, in Fig. 2a as a line 63, to which the B register 42 of the arithmetic and logic unit 11 are transferred. In the same way can also during the Α-time the content of a selected register in the A register 41 of the said arithmetic and logical Unit 11 will be transmitted.

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- Q -

To get the data from a register as shown in Fig. 2a, b is to be transmitted out, the first switching stage appears, when a register of the module is selected by means of line 47, 48 became. At this time, the value stored in the register latch circuits 53 of the selected register becomes from the corresponding AND gate 55 to the associated gate 86. When the clock 1 signal on line 80 goes negative (-CLK 1) (during the last three quarters of the A or B time), the values in the selected register bit storage positions switched through to the 8 lines, one of which, namely line 63, is shown, which lines are the bidirectional Form data path 22. This makes the number of logical Delays are kept extremely low, thereby reducing the time it takes to transfer data out of a register.

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Claims (1)

- ίο - PATENT CLAIMS Processor with a switching device for a bidirectional data line to connect the control part, arithmetic and logical unit as well as various data registers, characterized in that the data registers consist of binary storage locations (e.g. 52; Pig, 2a) for storing two binary levels each, the or absence of data indicate that further a register selection circuit for addressing one of several Registers that first switch for switching data through to the bus in the binary memory locations of a selected register during a first portion of an instruction cycle and that eventually second switch for switching through the binary levels stored in the binary storage locations of a selected register are provided on the data line, 2, processor with a switching device according to claim 2, characterized in that the second switch means of a first gating level, the binary levels from the binary memory of a selected register to a first one Gate and by means of a second switch-through level said binary level from the second gate to the common one transmit bidirectional data line. 3, processor with a switchover device according to claim 1 and / or 2, characterized in that the binary storage locations have an interlocking circuit that is set for specifying a first binary level and for specifying a second binary level. 4, processor with a switching device according to an or several of claims 1 to 3, characterized in that a group of registers on a circuit module is arranged and an interlock circuit and a 509812/0990 first gate is provided for each register bit position and a second gate for each module output bit position, the first gate the setting of a during a first instruction cycle section selected module register from the common bidirectional data line and the second gate the transmission of binary levels of the bit positions of a during a second instruction cycle makes the selected register on the common bidirectional data line, Processor with a switching device according to one or more of Claims 1 to 4, characterized in that that several registers are arranged in a circuit module and with the other elements of the processor via a common bidirectional data line exchange information, each data register being a series of binary Storage locations and gates for the selection of one of several registers and first gates for switching through binary data from the data line to a selected register during a first instruction cycle portion to set a number of binary storage locations according to the binary data and finally second Includes gates that occur during a second instruction cycle portion the switching through of the binary stages that are required for the binary data in the memory locations of one of the selected register is indicative, to the common bidirectional data line, Processor with a switchover device according to one or more of Claims 1 to 5, characterized in that that the second gates have a first stage in which a series of first gates each have binary stages of the binary Switch through register storage locations each to a series of second gates and a second switching stage have, in the second row of goals the ⁹⁷³⁰¹⁵ 609812/0990 transfer the said binary levels to the common bidirectional data line, 7. Processor with a switching device according to one or more of claims 1 to 6, characterized in that that the rows of binary storage locations each contain a locking circuit which is set, to represent a first binary level and reset to represent a second binary level. 8, processor with a switching device according to one or more of claims 1 to 7, characterized in that that the circuit module is connected to several data lines, the number of which corresponds to the number of binary Storage locations in a register coincide, with the plurality of data lines connecting the said Circuit module with the bidirectional data line and both the line for the input data a selected register during a first instruction cycle portion as well as for the output data during of a second instruction cycle section. 9 »Processor with a switching device according to one or more of Claims 1 to 8, characterized in that that the circuit module is further connected to a plurality of register selection lines, the signals of which in the circuit module can be decoded to select one of the registers in that module and with a single module select line is connected to select the appropriate circuit module. RO 973 015 509812/0990