SU1532926A1 - Microprogram dispatcher of multiprocessor computing system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multiprocessor computing systems. The purpose of the invention is to expand the field of application of the device due to the possibility of redistributing tasks between processors. The multiprocessor computing system microprogram manager contains a microprogram control block, a queue block, a task number code register, a processor number code register, a register of serviced backups, a processor readiness register, a start trigger, a group of control triggers, a switch, a control decoder, two elements And a group of elements AND, a group of blocks of elements AND, two elements OR, a decoder for queue management, a group of elements OR, a group of registers that are serviced separately, a multiplexer before maintenance them- wok, logical block forming conditions. 1 hp f-ly, 5 ill.

Description

The invention relates to computing and can be used in the construction of multiprocessing computing systems.

The purpose of the invention is to expand the field of application due to the possibility of redistributing tasks between processors.

Figure 1 shows the functional diagram of the device; Fig. 2 is a block diagram of a queuing queuing block; in FIG. 3, a schema of a block for the formation of logical conditions; FIG 4 is a timing diagram of pulses generated by a clock pulse generator; FIG. 5 is a block diagram of a device operation algorithm,

The device contains block 1 of firmware memory, block 2 queues of the request, register 3 addresses of micro-instructions, register of 4 micro-instructions, register 5 of the task number code, register 6 of the code for the number of processors, group of registers 7 of the serviced requests, register 8 of processor availability, trigger 9 start, control trigger group 10, logical conditions multiplexer 11, address multiplexer 12, pre-service multiplexer 13, switch 14, pre-service decoder 15, decoder control decoder 16, element 17, element group I 18, element group comrade AND 19, AND gate 20, an OR 21 group elementen

with y

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com or 22, element OR 23, logical conditions-forming unit 24, generator 25 clock pulses, group of inputs 26 operation codes, group of inputs 27 codes of the first type, start input 28, group of inputs 29 external logic conditions, groups of inputs 30 codes a second type of input, a group of inputs 31 of processor readiness signals, a group of outputs 32 task number codes, a group of control outputs 33, a group of outputs 34 micro-operations, a group of control outputs 35, a group of address outputs 36 of microprogram memory block 1, controlling | move 37 devices, ne 38 and second 39 outputs of the generator 25 clock pulses, output 40 for terminating the mode, group of outputs 41 for queuing control signals, output 42 for switching control, group of outputs 43 for managing additional servicing of microcommand register 4, first 44, second 45 and third 46 outputs decoder 16 queue management, a group of control outputs 47 of the block 2, a queue of the request, the first 47.1, the second 47.2, the third 48, the fourth 49, the fifth 50.1, the sixth 50 and 2, and the third 51 inputs are internal-; The logical conditions of the multiplexer are 11 logical conditions. Moreover, blocks 11, 12, 3, 1, 4, and 16 form a microprogram control unit. Block 2 of the queue for the wok contains a group of registers 52 queues of the wok, the first 53 and the second 54 groups of elements AND, element AND 55, element OR 56, element AND 57, element AND 58 and the group of triggers 59o

The logical condition block 24 consists of the group of elements OR 60, the element OR 61 and the element AND 62 "

The device works as follows.

In the initial state, the device registers and triggers are set to the zero state with the exception of register 8, which is in the single state, which indicates that the processors are ready for the task

According to the start signal received at the input 28 of the device, the trigger 9 is set to one. At the same time, at outputs 38 and 39 of generator 25, the formation of a clock pulse grid in accordance with

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with time diagrams shown in FIG. 4 o

Simultaneously with the start signal, the operation code and application code, respectively, are supplied to the device inputs 26 and 27

The operation code determines the starting address of the task scheduling control firmware, and the application code determines the number of the corresponding task and the number of processors to execute it.

The device implemented queues for two types of wok

Applications of the first type are applications, the first time the service codes of these applications are stored in registers 52 of block 2 "

Applications of the second type are those that, after receiving a quantum of service on the processors, are returned for additional maintenance to the device; These codes are stored in registers 7.

Depending on the dispatching firmware implemented, the following disciplines of priority interaction between the first and second types of queues are possible:

The priority of service belongs to applications of the first type,

In this case, if there is a queue of the request in block 2, the devices are serviced only by the requests of this queue, and service of the second type of call is possible only if in block 2 the queue is empty. This mode is expedient to use in those cases when the intensity of arrival of applications of the first type is low and they require a small number of processors. The priority of service belongs to the second type of application. In this case, if in registers 7 there are applications for additional services, then only these applications are serviced by the device, and applications of the first type are serviced when the device is not required for additional maintenance. This mode is expedient to use in the case when applications of the second type require a large number of processors, and the flow rate of applications of the first type is high or they require a long time to occupy the system processors.

In those cases when the flow characteristics of the first and second types of the flows are not defined, it is advisable to use the equal priority mode.

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queue service. In this case, queuing requests are selected alternately for maintenance.

The described operating modes of the device correspond to the discipline of servicing the queues in accordance with relative priorities. Along with this, it is possible to service the queues in the device according to the discipline of absolute and mixed priorities “

The preferred service of the second type bids (Fig. 05).

The clock pulse from the output 38 of the generator 25 into the register 3 records the operation code of the corresponding control firmware, which is received from the input 26 of the device through

15, a signal is generated at the output 44, then at the output 45, then at the output 46 of the decoder 16. The execution of the microoperations determined by the listed signals is carried out according to

Tiplexer 12 "In this case, the setting for zero-20 pulses from the output 38 of the generator of the typlexor 12 is determined to be zero 25.

code at output 33 of block 1 “The code one- Consider the recording of the application from the input of the radio sets the starting address of mic- 27 block 2 in register 52.1. By the control program. The reading of the unit potential at this address is a microcommand from block 25, input 44, block 2, and a clock pulse

From the input 38 of the unit 2, the zeroing of the flip-flops 59 is carried out. This ensures that the queued quotes are saved and their duplicates are destroyed.

The code for the input from the input 26 of block 2 is fed to the input of the register 52.J, and the sign of the presence of the application to the input of the AND 54.1 element. Since the register 52.1 is in the zero state, it follows the logical condition on the input signal from input 45 and the pulse from input 50.1, and the request of the first type is recorded in

1 defines the performance of the following functions in a device in accordance with the operation algorithm shown in Fig. 05.

The decisive condition for the operation of the device in this mode is the presence of the second and first types of applications in the corresponding queues.

Presence of the second type of requisite for the diagnostic condition at the input 47.2 of the multiplexer 11 "

1 l

In case of fulfillment of the condition LU50.1 "LU 51 1 (), the device implements the process of servicing the second type of bids. If the condition LU50 is fulfilled. LU51-LU47.1 1, (2) then the device implements the process of recording the first type of application in the queue of block 2o

When satisfied

38 of block 2 of the application is recorded in register 5201. "At the same time, at the output of the sign of the presence of the application of this register, a single potential is established

4Q prohibiting, recording the application to this register in the next clock cycle. Since the trigger 59.1 is set to the zero state, the register 52.1 on the clock pulse from input 38 when the 45 input signal 46 is not reset does not occur.

V. The next write cycle of the application to queue 2 of the register from register 52.1 is rewritten to register

ЛУ50 „1 ЛУ47.2 ЛУ51 - 1

(3)

servicing of the first type of request is performed; at the same time, the first type of applications received for service from the device input 27 are recorded in the queue of the 2 "block

The condition for shutting down the device corresponds to the condition

ЛУ50, ЬЛ47.2 ЛУ51 ЛУ48 1. (four)

At the initial phase of operation of the device, the first true condition among the tested ones is the condition LU47.2 LU4701 1. In accordance with this, consider the implementation of the function of recording the first type request to the queue of block 2 "

In this mode of operation

0, at the output 42 of register 4, a single potential is accepted, and at the output 41 of this register, codes of queue control signals are sequentially generated. And at the beginning

a signal is generated at output 44, then at output 45, then at output 46 of the decoder 16. The micro-operations, determined by the listed signals, are performed according to the

0 output pulses from the output 38 of the generator 25.

The code for the input from the input 26 of block 2 is fed to the input of the register 52.J, and the sign of the presence of the application to the input of the AND 54.1 element. Since the register 52.1 is in the zero state, the signal from input 45 and the pulse from input 2 are recorded in

38 of block 2 of the application is recorded in register 5201. "At the same time, at the output of the sign of the presence of the application of this register, a single potential is established

Q prohibiting, recording the application to this register in the next clock cycle. Since the trigger 59.1 is set to the zero state, register 52.1 is not clocked at input 38 when there is a 5 input signal at input 46.

V. The next write cycle of the application to queue 2 of the register from register 52.1 is rewritten to register

0 52.2, if it is not occupied by another application. In this case, the trigger 59.1 is set to one, which provides the possibility of zeroing the register 52.1 and destroying the copy

5 for vki.

The choice of service request is made from the register 52.L0 In this case, the input 42 of the unit 2 is set to zero potential, which ensures

installation of the trigger 59 .L in one state and in the subsequent zeroing of the register 52.L,

If all registers 52 of block 2 are content, then at output 47.1 of the element C 55 there is a unit potential, according to which it is forbidden to write a quota to the queue. 1 If at least in one register 52.1 "| application for service, on the benefit of 47.2 of the element OR 56 there is a single potential, according to which the sample of the quota from the queue is allowed, but | service

After completion of the write cycle per in-queue, the device performs a sequential check of conditions (1) (4).

Suppose that in the next cycle of checks of logical conditions the following condition was fulfilled (1) о But this condition in the device implements the process of servicing the second type of application.

When servicing the second type of bays, a single potential is established at the output 42 of the register 4, and a sequence of codes is controlled at the output 43 that control the configuration of the multiplexer 13 and the decoder 15, the application code from one register 7 goes through the multiplexer 13 to the input of the switch 14 and is further recorded in registers 5 and 6 under the influence of a clock pulse from the output 38 of the generator 25, after which a single pulse is formed at the corresponding output of the decoder 15, setting the corresponding trigger 10 and the register 7 at zero new state "

One of the service phases of the applications of the first and second types is their distribution among the processors of the computing system.

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those. if the K-th bit of register 6 contains one, the K-th processor is free and the trigger 10.K is set to the zero state.

When the listed conditions are fulfilled, the outputs of the corresponding block of elements I 19 are set. The code of the task number is set, which enters the processor field from the outputs of 32 "K devices. When the above distribution conditions are met, it is possible to simultaneously assign a processor group to a task.

In the case when the K-th processor was assigned, for solving the problem, the output potential of the corresponding element OR 22 "K is set to a single potential, according to which the corresponding K-bits of registers 6 and 8 are set to the zero state. In the future, the corresponding processor cannot be assigned to solve the task until complete release. Simultaneously with assigning the K-th processor to solve the task from the queue of the block 2, the corresponding trigger 10.K is set to one. The purpose of this function in the device is explained in the description of the service of the second type of bids,

The distribution of tasks among the processors in the device is carried out as long as there are free processors in the system and there are requests for solving in the queues of block 2 and group of registers 7

When allocating tasks from the queue of block 2, there are the following features. A task that defines a system control program can be distributed to more than one processor. Due to the fact that

type of phase, this phase has some special stage of operation of the device, yes, all the processors in the system are free, the required number of processors

After writing the code of the task number in register 5 and the code of the number of processors in

task is assigned simultaneously

Subsequent distributions

in register 6 at the output of 51 elements OR 50 tasks, the following situations are possible. 23, a single potential is established after writing the code of the number of processors al, which prohibits writing to registers 5 and 6, and allowing execution of the shift of the contents of the register 6 „

The assignment of the Kth processor to task 55 is accomplished under the following condition

In register 6, the assignment of the corresponding processor to the task is impossible due to its busy state. In order to ensure that the task is distributed to other processors, a circular shift of the contents of register 6 is carried out for the purpose of finding a free processor in such a way. 6.K 10.K-8.K 1,

The following situations are possible. After writing the code number of processors

In register 6, the assignment of the corresponding processor to the task is impossible due to the state of its occupied state. To ensure that the task can be distributed to other processors, a circular shift of the contents of register 6 is performed for the purpose of finding a free processor. Thus, the task is distributed among the processors until all the required processors are assigned. The process of assigning tasks to zero all of the bits in the register 6 is completed.

When performing servicing of the second type of bids, the device implements the following processes: formation of the second batch of the second type in registers 7; release of processors; distribution of tasks from the queue of additional tasks by processors,

Consider the process of forming the queue of the second type of queuing. Upon the completion of the task at the first service phase of the request, the corresponding K-th processor places a code on the corresponding inputs of the 30 K device, and also generates a readiness signal at the input. 30 „K. In this case, the code of the application is recorded in the register 7 К K and the readiness of the unit readiness potential of the K-th digit of the register 8 is restored. If there are applications in registers 7, the unit potential that is checked is found at the output 50 1 of unit 24 logic multiplication 50.1 11.1.

In the event that the processor has completed the task and no further service is required, then the application code is not entered into the corresponding register 7, and the processor’s readiness to perform other tasks is restored in register 8 by the ready signal.

The device is terminated when the condition (4) is met. In this case, the final micro-command is read from block 1. At output 40, register 4 of this; microinstructions set a single potential. In the next cycle, the pulse from the output 38 of the generator 25 at the output of the element 17 forms a single pulse prohibiting the formation of a clock grid of pulses at the outputs of the generator 25.

Claims (2)

1. A microprocessor controller of a multiprocessor computing system containing a queue for a queue, a task number code register, a processor number code register, a register that is serviced by a processor, a processor ready register, a start trigger, a group of control triggers, a switch, a control decoder, the first and the second elements Kf are a group of elements AND, a group of blocks of elements AND, the first and second elements OR, a decoder of the queue management, a group of elements OR, and the start input of the dispatcher is connected to a single input of the start trigger The output of which is connected to the start input of the clock generator, the group of outputs of the register of the processor number code is connected to the group of inputs of the first OR element, the outputs of the elements OR of the group are connected to the first inputs of the corresponding AND elements of the group, the group of readiness of the processor’s processors is connected to the group of single inputs of the register processor availability, the group of inputs of the first type of device code is connected to the group of inputs of the queue of the queuing unit, which is designed to expand the due to the possibility of redistributing tasks between the processors, a microprogram control unit, a group of registers under maintenance served, a multiplexer under maintenance servicing, a logic condition generation unit are entered into the dispatcher, the dispatcher operation code input group is connected to the first group of information inputs of the microprogram control unit, the output of the completion of the mode of which is connected to the first input of the first element I, the group of outputs of the queue control signal signals of the microprogram block control unit is connected to a group of inputs of the decoder of the queue control decoder, the first, second and third outputs of which are connected respectively to the reset inputs, recording and control of the recording of the queue block, the output of the control commutation of the microprogram control unit is connected to the input of the shift control of the queue block for wok, s the control input of the switch and with the second inputs of elements AND of the group, the group of outputs of the control of additional servicing of the charge of the microprogram control block is connected to the group of information inputs into the decoder control-. with the group of control inputs of the multiplexer pre-maintenance, the group of outputs of which is connected to the first a group of information inputs of the commutator, a group of information outputs of the block of the queue of the request are connected to the second group of information inputs of the switch, a group of outputs to (yes the task numbers of which are connected to & a group of information inputs of the register of the task number code, and a group of outputs of the code processors - with a group of information of the inputs of the register of the code of the number of processors, the first output of the clock pulse generator is connected to the first synchronization input of the microprogrammed control unit task omer, register of the number of processors, block of the queue for the wok, strobe input of the after-care decoder and the second input of the first element K, the output of which is connected to the zero trigger start input, the second output of the clock generator of the microprocessor control, the first and the second outputs of the characteristics of the filling of the queue of the queuing block are connected respectively with the first and second inputs of the internal logic conditions of the microprogram control unit, the output of the recording indication the block queue request is connected to the dispatcher output signal YYm, the output of the first OR element is connected to the shift enable input and the enable input of the cctopojj number register code register, and the the third input of the internal logic conditions of the firmware control block is the group of outputs of the register of the code of the code of the task number connected to the groups of inputs of the blocks of elements AND of the group, the groups of outputs of which are connected with the corresponding groups of outputs of the codes of the number of tasks of the dispatcher and with groups of inputs of the corresponding elements OR groups whose outputs are connected to the corresponding zero inputs of the processor readiness register, the group of outputs of the register of the number code of the processors is connected to the first inputs of the blocks of elements AND groups, the group of outputs of the control decoder is connected to zero inputs of the register of the secondary control groups and control triggers groups, the inverse outputs of which are connected to the second inputs of the corresponding blocks of elements AND groups, the group of outputs of the processor readiness register in connected with the third inputs of the blocks of elements AND of the group and with the inputs of the second element OR and the second element AND, the output of which is connected to the fourth input of the internal logic conditions of the microprogram control unit, the output of the second element OR is connected with the fifth input of the internal logic conditions of the microprogram control unit the inputs of codes of the second dispatcher type are connected to the groups of inputs of the corresponding registers of the further maintained orders of the group, whose output groups are connected to the groups of information in repetition multiplexer moves and with input groups of the logical condition generation unit, the first and second outputs of which are connected respectively to the sixth and seventh inputs of the internal logic conditions of the microprogrammed control unit, the input group of external logic conditions of the dispatcher are connected to the second information input of the microprogrammed control unit. 2. The dispatcher according to claim 1, characterized in that the logical condition generation unit comprises a group of OR elements, the AND, OR outputs of which are the first and second outputs of the block, respectively, the groups of inputs of which are connected to the inputs of the OR elements of the groups whose outputs are connected to the inputs of the AND element and the OR element. Faye. one rirTti XR A / f P Ј " ( Start } . I I cop - + - to & w - 0