SU1151966A1 - Device for distributing jobs among processors - Google Patents

Abstract

A device for assigning tasks to processors containing a group of storage registers, a shift register, a processor readiness register element OR, a group of blocks of elements AND, a block of elements AND, a first element AND, a group of elements OR, and a group of information inputs of the device group, the group of outputs of each register of the group's storage - with the group of inputs of the next group's storage register, the group of outputs of the last group's holding register - with the group of inputs An element of elements And, a group of outputs of each block of elements And is connected to a group of inputs of the same name of the group II element and is a corresponding group of outputs of the device, the outputs of the elements of OR group are connected to a group of inputs of the reset of the shift register and a group of inputs of the reset of the register of readiness of processors, each output output the shift register is connected to the first input of the same-name block of elements of the AND group. the outputs of the shift register are connected to the inputs of the OR element, each signal input of the device is connected to the same information input of the processor readiness register, characterized in that, in order to improve speed, the device contains a trigger, a pulse generator, a group of blocks of the AND-OR elements, a group of decoders, a group the service registers, the one-shot, the second and third elements AND, and the element OR NOT, the output of which is connected to the first input of the first element AND whose output is connected to the zero input of the trigger, the output of the OR OR connect (L is not with the first control inputs of the AND-OR group blocks, with the first input of the BL-NOT element, with the inverse input of the AND element block, with the shift offset input of the shift register and with the one-shot input, the output of which is connected to zero the input of the last storage register: l group, the outputs of the signs of the presence of registers of storage of the group with are connected respectively to the inputs Od O) of the element OR NOT, the output of the sign of the presence of the application of the last storage register of the group is connected to the inverse input of the second element a And, the output of the sign of the presence of the first storage register of the group is connected to the first input of the third element And whose output is the signal output of the device, the first output of the pulse generator is connected to the second inputs of the first and third elements And, the second output of the pulse generator is connected to the resolution input register entries

Description

shift, with clock inputs of service registers of the group and with the second input of the second element And, the output of which is connected to the clock inputs of the storage registers of the group, the group of outputs of the block of elements And connected to the group of information inputs of the shift register, with the first groups of inputs of blocks of elements AND-OR of the group, The second control unit input of each block of the AND-OR group of elements is connected to the corresponding output of the group of outputs of the AND block of the elements, the group of outputs of each block of the elements of the AND-OR group is connected to the group of informational inputs the group's service register of the same name, the group of outputs of each service register, the group, except the last, is connected to the second group of outputs of the next block of AND-IPI groups, the group of last service outputs of the group is connected to the second group of inputs of the first block of AND-OR groups, the group of outputs of each the service register of the group is connected to the group of inputs of the same name decoder of the group and with the group of inputs of the same name block of elements AND groups, each output of the group of outputs of the readiness register process The first input is connected to the second input of the same name block of elements AND of the group, the third input of each block of the element AND of the group is connected to the output of the same decoder of the group, the reset input of each service register of the group is connected to the output of the same name of the OR group, the start input of the device is connected to the single trigger input, output the last bit of shift is connected to its first information input.

The invention relates to computing and can be used to build multiprocessor computing systems. A device for assigning tasks to processors is known, comprising a processor readiness register, a group of elements AND, a shift register control unit, processors, and OR elements l. The disadvantages of this device are low reliability due to the existence of a high probability of loss of application for solving the problem caused by the failure of the device to perform the task in the case when the number of free processors is less than the number of required processors; limited functionality, which is manifested in the fact that the device lacks the ability to organize a queue of tasks. The closest to the invention is a device for distributing applications among processors, containing a group of storage registers, a group of outputs indicating the number of required processors of the last storage register of a group, a group of inputs of an indication of the task number of the first storage register of a group, a group of inputs of the number of required processors of the first storage register of a group , first and second groups of elements AND, element AND, shift register, information input of shift register, element OR, block of elements OR, group of processors, register processor availability, the control unit, the first input of which is connected to the device start input, the output group of the processor readiness register is connected to the first inputs of the AND elements of the first group, the second inputs of which are connected to the output group of the shift register and the input group of the OR element whose output is connected to the second input control unit and the first input element And, the second input of which is connected to the output of the higher bit of the output group of the shift register, the output of the element And is connected to the shift input of the shift register, input which is connected to the output of the OR block and to the reset input of the processor readiness register, the group of information inputs of which is connected to the outputs of the group of processors, whose outputs are connected to the outputs of the AND elements of the first group and to the inputs of the block of OR elements, the control input of the shift is connected to the first the output of the control unit, the group of information inputs of the first register of the storage group is connected to the group of inputs behind the device, the control input of each register of the storage group is connected to the output according to The second element of the second group, the group of information codes of each storage register of the group, except the last, is connected to the group of information inputs of the next group's storage register, the first input of each element of the second group, except the last, is connected to the output of the next element AND of this group the first input of the last element And the second group is connected to the second output of the control unit i2j. A disadvantage of the known device is low speed. The purpose of the invention is to increase the speed of the device. , The goal is achieved by the fact that in a device for distributing tasks to processors, it contains a group of storage registers, a shift register, a readiness register, a processor, a group of processors, an N1SH element, a group of AND blocks, an AND block, an AND element, an OR group of information the device inputs are connected to the group of information inputs of the first storage register group, the output group of each perHcjrpa storage group with the input group of the next storage register group, the output group of the last the storage register of the group is connected to the group of inputs of the block of the elements AND each shift output of the shift register is connected to the first input of the block of the same name and group; the outputs of the shift register are connected to the inputs of the OR element, each the signal input of the device is connected to the informational input of the processor readiness register of the same name, a trigger, a pulse generator, a group of blocks of AND-OR elements, a group of decoders, a group of service registers, a single vibrator, a second and a third elements of AND, and a HW-NOT element whose output is connected to the first are entered the input of the first element AND, the output of which is connected to the zero input of the trigger, the output of the element OR is connected to the first control inputs of the blocks of the elements of the AND-OR group, with the first input of the element OR NOT, with the inverse input of the block And, with the shift register shift input and with the one-vibrator input, the output of which is connected to the zero input of the last group's storage register, the outputs of the signs of the group's storage registers are connected respectively to the inputs of the OR-NOT element, the sign of the presence of the last register the group storage is connected to the inverse input of the second element AND, the output of the indication of the presence of the first group storage register is connected to the first input of the third AND element whose output is the signal output The device's home, the first output pulse generator is connected to the second inputs of the first and third elements, And the second output of the pulse generator is connected to the write enable input of the shift register, with ticks. the inputs of the service registers of the group and the second input of the second element I, the output of which is connected to the clock inputs of the registers of the storage group the input of each block of the I-ILI group elements is connected to the corresponding output of the group of outputs of the AND block of the elements, the group of outputs of the block of the block of elements of the AND-OR group is connected to the group of information inputs of the same name region The service group of the group, the group of outputs of each service register of the group, except the last one, is connected to the second group of outputs only 51

the next unit of the AND-OR group of the group of outputs of the last service register of the group is connected to the second group of inputs of the first block of the AND-OR group, the group of outputs of each group's service register is connected to the group of inputs of the same name decoder group and the group of inputs of the same block of elements AND group, each the output of the group of outputs of the processor readiness register is connected to the second input of the same name block of elements AND of the group, the third input of each block of elements of the AND group is connected to the output of the same name the encoder of the group, the reset input of each service register of the group is connected to the output of the element of the same name OR group, the device start input is connected to the single trigger input, the output of the last bit of the shift register is connected to its first information input.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 is a schematic diagram of the operation of the device.

The device (Fig. 1) contains a group of information inputs 1 of the device, an input 2 of the start of the device, a signal output 3 of the device, elements AND 4-6, element OR-NOT 7, element OR 8, block 9 elements AND, group of blocks 10.1-10. N elements AND, group 11.1-11.N element blocker, group 12.1.12N elements OR, group 13.1-13.N decoders, trigger 14, one-shot 15, pulse generator 16, outputs 17 and 18 of pulse generator 16, group 19.1-19 .L storage registers, shift register 20, service registers group 21.1-21.N. Processor readiness register 22, group 23.1-23.N processors, group 24 of the outputs of the elements of block 9 elements. Comrade I, 24.1-24.K-first, N-th bit of group 24 outputs of block 9, group of outputs 25.1-25.N of registers 21.1-21.N, outputs 26.1-26.L of signs of the presence of application registers 19.1-19 .L.

A start signal is applied to the input 2 of the device, which brings the device into a working state. Output 3 is used to retrieve a receipt for the entry system in group register 19.1 to the local system.

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The group of registers 19.1-19, L of the storage device is intended for organizing a queue of requests for servicing. The recording of the request is made in the first register 19.1 of the group, and the selection of the application for service is made from the last 19. L of the group storage register in the parallel code.

Service registers 21 are designed to store the characteristics of the task number and the available processors in the process of allocating the processors to the task. Shift register 20 is intended to store the processor number code, which is represented in the position code. The presence of a unit in this code indicates the need. distribution processor. task. Readiness register 22 is intended to register processor readiness signals. A single register bit indicates that the processor is free and can be distributed.

In the initial state, all the memory elements, except the processor readiness register 22, are in the zero state, and the processor readiness register 22 is in a single state, which indicates the readiness of the processors 23.1-23.N to solve the problem. The input 2 of the device receives a start signal, by which the trigger 14 is set to one state and allows the signal to pass through the element 5 from the output 18 of the generator 16 to the clock inputs of the registers 19.1-19. B. Simultaneously with the start signal at the outputs 1 of the device, the application goes, which, under the influence of the signal from the generator 16, is written into the register 19.1. After that, a receipt from the queue for receipt of the entry into the queue is issued according to the cycle from the output 17 of the generator 16 to the output 3 of the device. Promotion of the application in registers 19 is carried out until such time as the application is not recorded in the last register 19. During the promotion of applications in registers 19 and the device inputs 1, sequential applications can be submitted which are also recorded in registers 19.. Thus, in registers 19.1-19.L a queue of requests for the most up-to-date tasks is formed.

After writing the application to the last register 19 at the output of 26.1 of the last register 19.L, a signal of the presence of the application is established, which prohibits the signal from passing through the element 5. After writing the first application to the register 19.L, it is selected for service, the essence of which consists in assigning the required number of processors to the problem to be solved. The selection of the service request from register 19, L is made whenever there are applications in the queue and the device is not occupied by the service. A signal that the device is not occupied by the service is generated at the output of the element OR 8, if in register 20 all bits are set to the zero state. At the beginning of the operation of the device, register 20 is in the zero state and, therefore, zero potential of the element OR 8 output is opened. Block 9 elements I. After recording the application in register 1.9.L, at the outputs of block 9, the application code is set, which determines the number code processors required to solve the problem (at outputs 24) and the task number and processor availability codes, since zero potential is set at the input of the register shift enable 20, the clock pulses from the output 18 of the generator 16 entering the write enable input are set to control and 20 L of a recording implement parallel code output unit 9, 24 in the register 20. In addition, clock output 18 of the generator 16 fed to the clock inputs of registers 21.1- -21 .N. At the same time, the info inputs of these registers of blocks 11.1-11, K are used for input 24 only for those registers that correspond to the unit state of the corresponding bit 24.1-24.N. Thus, according to the next clock pulse from the output 18 of the generator 16, the code of the number of processors and register 20 is written, and in registers 21.1-21.N - the codes of the task number and the availability of processors are recorded. After writing the code, the number of processors in register 20 at the output of the element OR 8 is set to single

the potential, but which closes the block of 9 elements AND, outputs 24 from the inputs of the registers 21.1 tons. The processor availability code is defined for the corresponding decoder 13. When all the 212Ns are executed, N, and for these registers, through blocks 11.1-11 .N, circuits are formed to cycle the contents of registers 21.1-21.N from the first to the last, and the output of the last register is 21. N is connected to the input of the first register 21.1. The input to the resolution of the shift register 20, a single potential from the output of the element OR 8 prohibits recording on the information inputs of this register and allows cyclic shift of the contents of the register 20 in the direction from the first bit to the last, and the output of the last bit of the register 20 is connected to the input of the first bit Yes. This allows multiple attempts to allocate processors to a task. In addition, when the output potential of the element OR 8 changes from zero to one by one-shot 15, a pulse is generated, according to which the last register 19.L is set to the zero state. In this case, the clock pulses of the generator 16 are allowed to pass through the element 5, which controls the recording and promotion of the requests in the registers 19.1-19.N. Consider the operation of the device according to the purpose of the processors, the task defined by the selected application for service. In this case, it is advisable to consider the operation of the device in two stages: initial assignment of processors; subsequent assignment of processors. The initial assignment of processors is carried out in the following manner. From the outputs of the processor readiness register 22, the readiness signals arrive at the inputs 10I-10.N of the elements I. Signals from the register 20 outputs and the task number codes from the outputs .25.125 .N of the registers 21 arrive at the same blocks. Signals from the buses 25.1-25. N, determining the availability codes of the processors, arrive at the corresponding decoders 13.1-13.N. At the output of the decoder 13, the signal appears in the event that the corresponding processor can solve the subtask of the distributed task.

9 ,

VIY at the inputs of blocks lO..N elements And from their outputs, signals of assignment of processors are removed, through which the corresponding bits in register 20 and the corresponding registers 21.1-21.N are zeroed through the elements OR l2.1-t2.N. Thereafter, the And elements are closed to the corresponding blocks 1O.1-1O.N.

Further, two situations are possible in the operation of the device: after the initial distribution, all the necessary processors are assigned to the task; after the initial distribution, not all the necessary processors are assigned to the task.

In the first case, the device completes the maintenance of the task in question and a scan signal is generated from the register 19.L above the one considered above. The device proceeds to service the follow-up application for solving the problem.

The second case corresponds to the second stage of processor assignment, which proceeds as follows.

In register 20, not all bits are set to zero, therefore, at the output of the element OR 8, a single potential remains, which corresponds to the resolution of the ring cyclic shift of the contents of the register 20 by clock

5196610

pulses from the output 18 of the generator 16. The same pulses control the ring cyclic shift of the contents of the registers 21.15 21.N. In this case, after each successive shift cycle, a processor distribution task is attempted, similarly to the above. This process continues until

10 not all required processors 23.123, N assigned to the task. As soon as the distribution of the processors is completed, the output potential of the element OR 8 is zero.

15 and a new application is selected for service from the queue. The device is terminated if there is no demand in the queue and the device is not busy

20 for vki. In this case, the output

of the element OR-NOT 7, a single potential is formed, which is fed to the input of the element AND 4. By a clock pulse from the output 17 of the generator 16,

25 actions to the other input element And 4, trigger 14 is transferred to the zero state, prohibiting the generation of clock pulses by the generator 16. In the future, the device is ready for a new cycle

0 work.

The application of the invention allows to increase the speed of the device.

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Claims (1)

DEVICE FOR DISTRIBUTING TASKS TO PROCESSORS, containing a group of storage registers, a shift register, a processor readiness register, an OR element, a group of blocks of AND elements, an element block AND, a first element AND, a group of OR elements, and the group of information inputs of the device is connected to the group of information inputs of the first register group storage, the group of outputs of each group storage register - with the group of inputs of the next group storage register, the group of outputs of the last group storage register - with the group of inputs of the ele And, the group of outputs of each block of AND elements is connected to the group of inputs of the same element OR group and is the corresponding group of device outputs, the outputs of the elements OR groups are connected to the group of reset register reset inputs and the group of processor readiness reset inputs, each bit shift register output is connected with the first input of the same block of elements AND groups, the outputs of the shift register are connected to the inputs of the OR element, each signal input of the device is connected to the same information input processor readiness register house, characterized in that, in order to improve performance, the device contains a trigger, a pulse generator, a group of blocks of AND-OR elements, a group of decoders, a group of service registers, a one-shot, the second and third AND elements and the OR-NOT element, output which is connected to the first input of the first AND element, whose output is connected to the zero input of the trigger, the output of the OR element is connected to the first control inputs of the blocks of the AND-OR elements of the group, with the first input of the OR-HE element, with the inverse input of the block element And, with the shift enable input of the shift register and with the input of the one-shot, the output of which is connected to the zero input of the last group storage register, outputs of signs of the presence of the application of the group storage registers 9961SU are connected respectively to the inputs of the OR-HE element, the output of the sign of the availability of the application of the last group storage register is connected to the inverse input of the second element And the output of the sign of the presence of the application of the first group storage register is connected to the first input of the third element And, the output of which is the signal output of the device, the first the output of the pulse generator is connected to the second inputs of the first and third elements AND, the second output of the pulse generator is connected to the input enable register entries> the shift, with the clock inputs of the group service registers and the second input of the second AND element, the output of which is connected to the clock inputs of the group storage registers, the group of outputs of the block of elements AND is connected to the group of information inputs of the shift register, with the first groups of inputs of the blocks of elements of the AND-OR groups, the second control input of each block of AND-OR elements of the group is connected to the corresponding output of the group of outputs of the block of AND elements, the group of outputs of each block of AND-OR elements of the group is connected to the group of information inputs group service register of the same name, the group of outputs of each service register group, except the last, is connected to the second group of outputs of the next block of elements of the I-IPI group, the group of outputs of the last service register of the group is connected to the second group of inputs of the first block of AND-OR elements of the group, group the outputs of each group service register are connected to the group of inputs of the group decoder of the same name and to the group of inputs of the same block of elements AND groups, each output of the group of outputs of the readiness register processors connected to the second input of the same block of elements AND groups, the third input of each block of the element AND groups connected to the output of the group decoder of the same name, the reset input of each group service register is connected to the output of the same element OR group, the device start input is connected to the single trigger input, the output of the last a shear discharge is connected to its first information input.