SU1327106A1 - Apparatus for distributing jobs to processors - Google Patents

Abstract

The invention relates to computing and can be used to distribute tasks by hardware in multi-processor computing systems. The purpose of the invention is to increase the speed of the device. The device contains a processor readiness register, two blocks of AND elements, registers, comparison circuits, four groups of OR elements, a task type decoder, a comparison block, two switching blocks, a group of AND elements, a group of prohibition elements, OR elements, a delay element, In the initial state The device contains information about the readiness of the system processors and the tasks assigned to the processors in the previous cycles of the device operation. The device is initialized by applying to its inputs a job number code, a job type code, the number of processors required, a job number code immediately preceding this one. If the required number of processors exceeds the number of ready-made processors of this type that are in the system, the task distribution is denied. Otherwise, the task is distributed among the processors, and the incoming task is distributed among the processors of the required type, which completed the task immediately preceding this one, and if the number of such processors is insufficient, the task distribution is carried out by any ready-made processors of this type. 2 Il. with S (L 00 th

Description

one . one

The device relates to computing and may be used in computing systems for distributing tasks among processors.

The purpose of the invention is to increase the speed of the device.

FIGS. 1 and 2 are a block diagram of the device.

The assignment of tasks to processors contains a group of registers L-l-, numbers of tasks (where k

and

 Zl m; is the total number of processors in

ici

system, ha. - number of i-ro type processors, n-number of processor types), input group 2 numbers of the immediately preceding device setting, group of comparison circuits, group of elements OR, group of elements AND, group of elements of prohibition, group of elements OR, group of blocks of elements AND 8, processor readiness register 9, zero inputs, device processor readiness registers, an OR element 11, an input group of a code for a number of device processors, a group of device type inputs 13, a group of inputs 14 device set numbers, the first group of inputs

 comparison unit, second group of inputs of comparison unit, comparison block 17, first 18 and second 18 switching blocks, register 19 number of processors, decoder 20, group of information inputs 21 of the first switching block, group of control inputs 22 of the first and second switching blocks, first group of outputs of the first switching unit, second group of outputs of the first switching unit, element OR 25, delay element 26, group of elements Р1ПИ 27, register 28 assigned processors, group of blocks of elements И., group of outputs 30 of the second switching unit ,, гр RTD elements OR 31, a group of outputs 32-32 unit number assignments inputs 33 and 34 knots comparator unit, the outputs of nodes 35 and 36 comparing unit, 37 units, -. 37n, ir. block of comparison, element OR 38, element 39 of delay, element AND 40, element NOT 41 group of elements NOT 42, group of elements AND 43, group of elements OR 44, nuiHv 45 logical zero of block 15

2025

271062

device fault output 46, switching unit nodes 47, switching unit logical bus 48, inputs 49–51 switching unit nodes, outputs 52–54 switching unit nodes, reset input 55 of the device’s assigned processors, OR unit 56 of the comparison unit node , element 10 NOT 57, element OR 58, elements AND 59 and 60, element RSHI 61 of the switching unit node, element AND 62 of the node of the comparison unit.

The device works as follows

The assignment of tasks to the computing system is carried out taking into account the type of the received task and information and control links. If to complete the incoming task more processors of a certain type are required than there are free precessors of this type currently in the system, the task is removed from the service, if necessary fewer processors than are available in the system, processors are assigned to accomplish this task, and processors are first assigned who have completed the task, not backhoes prior to this, and, if this need. tasks in the processors will not be satisfied, assignment of processors of this type from among the remaining ones, until they are completely satisfied, is performed;

As a result, the input of the OR 7 7 elements receives information on the availability of i-ro processors of the system. In this case, the state signal of the first i-ro type processor is fed to the input of the element OR 7, the second to the input of the element OR 7, etc. As a consequence, single signals appear at the outputs of those elements OR 7 that correspond to i-ro free processors of the type. Further, these signals arrive at the first group of inputs of the comparison unit,

In block 17, a comparison is made of the number of processors required by the job with the number of i-ro free processors available in the system,

In general, the state of the processors is reflected. combination of zeros and

thirty

35

40

45

50

55

31

units, for example, 01101 for five processors means: the first and fourth processors are occupied, which corresponds to zero in the ready register, the second, third and fifth processors are ready - for them the corresponding readiness register is set to one. The required number of processors for specifying the i-ro type is reflected in the number of units in the code bits starting from the left-first. For example, the combination 11110 means that the job requires four processors.

Comparison unit 17 converts the state vector of the i-ro type processors, i.e. code 01101 (for our example) is converted to code 11100, which characterizes only the number of i-ro type ready-made processors. Next, a comparison of the kodo is made.

Thus, at the inputs 15, -15. Comparison unit 17, a state vector of i-ro type processors is supplied. The basis of the comparison unit is an iterative network consisting of a matrix of nodes. Network nodes are identical — and consist of AND and OR elements (FIG. 1)

From the inputs, the signals arrive at the inputs of the 33 nodes of the first column of the matrix. The inputs 34 of the nodes 37, -37 of the first row of the matrix are connected to the input 45 of the block, which, in turn, is connected to the zero signal source. Thus, a zero signal is applied to the first input of the element AND 62 of the node 37 and to the second input of the element OR 56 of the same node.

If a single readiness signal of the first processor of the i-ro type is supplied to the input 15 of block 17, the first input of the OR element 56 and the second input

element And 62 node 37. At the output 35 of this node there is a zero transfer signal in the horizontal direction, which is fed to the input 33 of the node 37, then to the input 35 of this node etc., and the output 36 of the node 37. there is a single transfer signal in the vertical direction, which, go through all the elements .OR 56 of the first column, exit 36 of node 37 ,, appears.

If a single signal is also present at the input 15 of the block, then it is fed to the input 33 of node 37. And element 62 of this node is opened by

five

0

five

about

five

five

0

five

06

the first input with a single signal coming in the input 34 of this node, and then at the output 35 of the node 37, there appears a single transfer signal in the horizontal direction, which is fed to the input 33 of the next node 37. Since the input 34 of this node contains a zero transfer signal from the node 37.2, at output 35 of node 37j, j there will be a zero transfer signal. From input 33 of node 37, a single signal arrives at the first input of the OR element 56 of this node, then at the output 36 of this node passes through all the elements OR 56 nodes of the second column and appears on output 36 node 37

Thus, at the outputs of 36 nodes 37 of the last row, we obtain the transformed state vector of the processors, all units of which are shifted to the left border, and the number of free (ready) processors is reflected by the number of ones in the transformed vector.

This vector is fed to the inputs of the corresponding NOT elements of the group, inverted and fed to the first inputs of the corresponding AND elements. The inputs of these elements are given a code of the number of processors required by the job. Moreover, the required number of processors is also reflected by the number of units in the code, all units of which are shifted to the left border (for example, the code 1111110000 means that the task requires six processors).

Elements 43 and 43 perform a one-to-one comparison of the code of the number of ready-made processors with the code of the number of processors required by the task. If there are more ready-made processors than is required to set, then at the outputs of all elements AND there is a zero signal and, as a result, at the output of the last element OR 44 (and also a zero signal.

A similar situation is added when the number of processors ready is equal to the number of processors needed, i.e. at the output of the element OR 44 there is a zero signal.

If the number of ready processors, i-ro type in the system is less than the task requires, then at the output of the element OR 44 there is a single signal.

The signal from the output of the element OR 44 through the element NOT 41 is fed to the second input of the element 40, the first input of which is fed to the signal from the delay element 39, the delay time of the last element is chosen so that the transients on the elements of the comparison block have completed

A single signal appears at the output of block 17 in the event that the number of ready i-ro processors is equal to or greater than the number of processors required for its processing. Otherwise, a zero signal appears at this output.

If there are enough processors to perform the task, the leading edge of a single signal from the output of the comparison block 17 is allowed to write the code of the number of necessary processors from the device inputs to the register of the number of processors 19,

Single signals from the output of the register 19 of the number of processors through the element OR 25 starts the delay element. The signals from the outputs of the register of the number of processors at the same time arrive at the inputs of the first switching unit 18.

At the same time, the outputs of the AND elements are connected to the i-control inputs of the 6 6 prohibition elements, on the information outputs of which, from the readiness register 9, idle signals of i-ro processors are sent. Therefore, single signals are present at the outputs of those prohibition elements that correspond to the ready-made processes of i-ro type, but which have not been fulfilled in the previous cycle of the task immediately preceding this process. From the outputs of the prohibition elements, the signals arrive at inputs 15–22 of the second block 18. commutation.

Thus, the inputs of the first switching unit 18 are provided with processor readiness signals. i-ro type, and at the inputs - the code 20 of the number of required processors, which is expressed by the number of units in the code, and these units are shifted to the beginning of the register.

Switching unit 18 represents

25 is a two-dimensional iterative network containing mxm identical nodes 47,

To the inputs 49 of the nodes of the first column of the matrix, the number of required codes is supplied from the inputs 2 of the C-21 switch

To the inputs 22i-22 of this block of com- pters, mutations, signals were given from the output to the inputs to the 50 nodes of the first line of cops and groups. These matrix signals are supplied from the inputs as follows.

The code of the task number immediately preceding this one is sent to the input 2 of the device and further along, given to the first groups of inputs of all comparison circuits, to the second groups of inputs from the registers 40

Task ditch receives job number codes assigned by system processors during previous device operation cycles.

The signals from the outputs of the comparison circuit

switch i-ro type processor availability vector.

The inputs 51 of the nodes of the first line are connected to the input 48 of the switching unit 18, which, in turn, is connected to a zero signal source.

The node 47 of the switch 18 is a finite state machine without memory. If the signals at the inputs and outputs of node 47 are designated as follows: 49-X5 ZO-U, 51-Z, 52-U 53-Z, 54-x, then the system of logical functions is available at the inputs of the elements OR 4 45% of the functions performed by the node has the form

w

From the VPSODs of the OR 4 elements, 4 signals are sent to the first inputs of the AND elements, to the second inputs of which i-ro type processors are sent from the ready register. Single signals appear at the output of those elements AND 5 -5, which correspond to ready-made processors of i-ro type, which completed the task immediately preceding this one. The signals from the outputs of the elements And 5., - 5 "are fed to the inputs of the switching unit 18.

At the same time, the outputs of the AND elements are connected to the i-control inputs of the 6 6 prohibition elements, on the information outputs of which from the register 9 of readiness, signals of readiness of i-ro processors are sent. Therefore, single signals are present at the outputs of those prohibition elements that correspond to the ready i-ro processors of the type, but which were not fulfilled in the previous cycle of the task immediately preceding this process. From the outputs of the prohibition elements, signals arrive at the inputs 22 of the second switching unit 18..

Thus, the inputs of the first switching unit 18 are provided with signals of i-ro type processors, and inputs - the code of the number of required processors, which is expressed by the number of units in the code, and these units are shifted to the beginning of the register.

Switching unit 18 represents

is a two-dimensional iterative network containing mxm identical nodes 47,

processors, At the inputs of the 50 nodes of the first row of the matrix is fed from the inputs

switch i-ro type processor availability vector.

The inputs 51 of the nodes of the first line are connected to the input 48 of the switching unit 18, which, in turn, is connected to a zero signal source.

The node 47 of the switch 18 is a finite state machine without memory. If we designate the signals at the inputs and outputs of node 47 as follows: 49-X5 ZO-U, 51-Z, 52-U 53-Z, 54-x, then the system of logical functions X (Yv Z), Y Y.

:

Xv xy

It can be seen from the system of functions that the node provides for the propagation of signals in two directions: from top to bottom and from left to right.

Each i-ro processor in the switching unit 18 corresponds to a matrix columnJ and to each required processor — a matrix row. The presence of single signals at the inputs of the node 47v.t means: at the input 49, ime 71327106

request for a ready processor; 50 there is 1st ready pro

re to ra

When coinciding single signals of the k-ro request to the processor, arriving at the input 49 of node 47,., And the ready signal of the -th processor, the following occurs.

An element AND 60 of this node opens, at its output a single signal appears, which through the OR element of this node appears at the output 53 of the node. Further, this signal propagates through the next nodes of the given column and is allocated at the output 53 of the last column node. This means that the 1st processor is selected to perform the task. At node output 54, there is a zero signal that propagates in the horizontal direction and cannot change until it leaves the switch. This signal means that the request for the finished processor is satisfied.

Thus, if a task requires R processors of the i-ro type and there are exactly R ready-made processors of this type in the system, all of which have completed the task immediately preceding this one, then all these processors are allocated for the task. At the outputs there are single signals corresponding to the ready-made processors, and at all outputs of the switching unit 18 there are zero signals, meaning that as many processors as the processors have requested are assigned to the task.

If there are i-ro processors in the system that completed the task immediately preceding this one, more than the task requires (more), then there are zero signals at the outputs 23, -23, and exactly R ones at the outputs, which means: only R processors of all completed and completed tasks, the immediately preceding task is selected to complete the incoming task.

If the job requires R processors of the i-ro type, and in the system there are S processors of this type (R) of which only P processors (completed the job,

five

rarely preceding this, the device works as follows.

Switching unit 18 allocates all P processors to execute the task in accordance with the described above. At the outputs 23.-23 of the switching unit 18, there are single signals, meaning that the task need in the processors is not fully satisfied and it is necessary to continue the task distribution to any free processors of this type. In this case, single signals are present on

exits 23

p41 I

23,

+ h

. .., 23. switch 18. These signals are fed to the corresponding inputs 21, 21pt2, ..., 21d of the switching unit ISj. On the inputs of this block, there are signals of the readiness of processors of the 1st type, which in the previous cycle performed a task that was not immediately preceding the given task, i.e. any free i-ro type processors.

Thus, conditions are created for the operation of the switching unit 18.

The operation of the iBj block is similar to the operation of block 18,

0

five

0

five

0

five

-, therefore, at its outputs there appear single signals that indicate which of any free processors are allocated for the task, and the number of units at these outputs is equal to the difference R-P.

Thus, the selection of the required number of processors is carried out.

From the outputs and blocks, the signals arrive at the inputs of the elements OR 27-1-27. The outputs of the elements OR 27 27 „are connected to the installation inputs of the register of 28 assigned processors. At this moment, a single signal appears at the output of the delay element 26, which by the leading edge synchronizes the recording of information into the register 28. The delay time of the element 26 is chosen so that the transients in the switching blocks can complete.

At the same time, a single signal appears at output 46, meaning that the required number of processors are assigned to the task. If the system has ready-made processors of the 1st type less than the task requires, then a single signal at the output 20 of the comparison unit is not generated, the number of processors code is not recorded in the register 19 of the number of processors and, as a result, the output 46 of the device remains a zero signal which means that it is impossible to complete the task,

The signals from the outputs of the register 28 assigned processors are fed to the third inputs of the corresponding blocks of elements AND from the output of the first bit to the third inputs of blocks of elements AND 29 corresponding to the first processors of all types, from the output of the second bit to the third inputs of blocks of elements And 29 corresponding to second processor of all types, etc.

At the same time, the second inputs of all units of units And 29 tc ° are signals from the corresponding outputs of the assignment decoder 20, the First output of the decoder 20 is connected to the second inputs of the blocks of elements 29, corresponding to the processors of the first type, the second output of the decoder 20 to the second inputs blocks of elements And 29, corresponding to the processors of the second type, etc,

Thus, among all the blocks of elements AND 29 29, the blocks that correspond to those of the i-ro type that are allocated to perform the task are open. Due to this, at the corresponding outputs of the device, an assignment task code appears, which is transmitted to the corresponding processors, the Single signals from the outputs of the corresponding blocks of the AND elements, or the corresponding bits of the processor readiness register 9, are outputted to the zero state, and the output signal the element OR 11 sets the number of processors to zero. In addition, the job code issued for the corresponding; device, is written to the corresponding registers of the job number code C-1, (,,

When all the selected processors start executing the task, a signal arrives at input 5 of the device, which sets the register 28 to the zero state, and along with that from the inputs 2, 13, -13p, the corresponding codes related to the already distributed task are removed

Q 5

about 5 about

„

five

0

five

The device is reset. The next assignment CYCLE is completed.

Claims (1)

Invention Formula A task distribution device for processors, containing a processor readiness register, the first group of AND blocks, a group of job number registers, a group of comparison circuits, the first group of OR elements, a task type decoder, the first group of inputs of each comparison circuit of the group being connected to the corresponding group of inputs the numbers of the immediately preceding device reference, and the second group of inputs of each comparison circuit of the group is connected to the group of outputs of the corresponding register of the group setting, the group of outputs each block of elements AND of the first group is connected to a group of inputs of the corresponding element OR of the first group, with a group of inputs of the corresponding register of the group number, the output of each element OR of the first group is connected to the corresponding zero input of the processor readiness register, the group of outputs of the device task numbers is connected to the group of outputs of the corresponding block of elements AND of the first group, the group of single inputs of the processor readiness register is a group of state inputs of the device processors , the group of inputs of the device reference number is connected to the group of inputs of the corresponding block of elements AND of the first group, to the first input of which is connected the corresponding output of the decoder of the type of task, the group of inputs of which is the group of inputs of the type of device, characterized in that, in order to improve speed, a comparison block, first and second switching blocks, a register of numbers; 1a processors, a register of assigned processors, a second group of blocks of AND elements, a second, third and fourth groups of OR elements are entered into it, the group of elements AND, the group of elements of the prohibition, the first and second elements OR, the delay element, and the inputs of the j-ro element OR of the second group are connected to the j-th outputs of each block of elements AND the second groups (, tn; m is the number of processors of the same type), the output group of the task type decoders is connected to the input group of the blocks of elements AND of the second group, the input group of the block of elements AND of the second group is connected to the corresponding output group of the processor readiness register, the output of the j-ro element OR the second group is connected to the first input of the j-ro element AND group, to the information input of the j-ro element of the group prohibition, the second input of the j-ro element AND group is connected to the output of the j-ro element OR the third group, whose inputs are connected to the outputs schemes compared and the j-th group, the output of the j-ro element OR of the second group is connected to the j-th input of the first group of inputs of the comparison block whose second group of inputs is the group of inputs of the device processor number code and is connected to the group of inputs of setting the number of processors in the unit state the output is greater than or equal to the comparison unit connected to the input of the register entry of the number of processors whose output group is connected to the group of information inputs of the first switching unit and to the group of inputs of the first element OR, the output of the j-ro element AND group by The key to a control IQ g Q 25 JQ 10612 input of the j-ro element of the group prohibition and to the j-th input of the control inputs of the first switching unit, the output of the j-ro element of the group prohibition is connected to the j-th input of the control inputs of the second switching unit, the group of information inputs of which are connected to the first group of outputs of the first switching unit, the i-th output of the second group of outputs of the first switching unit is connected to the first input of the i-ro element OR of the fourth group, the second input of which is connected to the i-th output of the group of outputs of the second switching unit, the outputs of the ISh elements of the fourth group of A group of information inputs of the register of assigned processors, whose recording input is connected to the output of the first element OR via the delay element and the output of the device failure, the group of outputs of the register of assigned processors is connected to the second inputs of the blocks of elements AND of the first group, reset input of the number of processors connected to the output of the second element SHS, a group of inputs of which is connected to the outputs of the elements OR of the first group, the device reset input is connected to the installation input in the register of assigned processes sors. / - iSf 13p FIG. g Compiled by M, Sorochan Editor L. Veselovska Tekhred L. Serdyukova Proofreader Reshetnik ., and, .i, .i, "... -.-..- ------- ----- - Order 3390/45 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 “. - "- - - - - - - - - - - - - - - - - - - Production and printing company, Uzhgorod, st. Project, 4