KR880001200B1 - Circuit for allocating access to a demandshared bus - Google Patents

Abstract

The circuit for access allocatin to a number of demanding terminals is carried out for a shared collecting line in a priority determining process. Each demanding terminal remains in the demand competition only as long as each of its digits is higher than those of another terminal. After application of all digits only the terminal with the highest code remains in contention and engages the line. On application of a reversing signal to this core for a certain time period, each demanding terminal inverts each bit of its priority code applied during this period to the collecting line. The polarity core enables a change of normal hierarchy of the terminals.

Description

System for allocating calls to split request bus

1 is a simple block diagram illustrating an exemplary system element in which the present invention may be employed.

2 is a detailed view of the for loop of FIG.

3 is a timing diagram.

4 is a detailed view of an arbitrary logic circuit of FIG.

6 and 7 are schematic diagrams of a controller for applying a signal to an inverting bus.

* Explanation of symbols for main parts of the drawings

107: switch 100: controller

110: port 101: polarity bis

102: arbitrary bus 103: clock bus

105,106: packet bus 200: input / output interface

210: input bus interface 220: output bus interface

120: data processor 218: arbitrary logic circuit

400: shift register 214: FIFO controller

The present invention relates to a system for assigning a call to a split request facility of a plurality of units, each unit having a unique n-digit priority number, the system comprising a system controller, an arbitrary bus interconnecting all units, In each unit requesting a call for a split request, an overlapping network is provided which sequentially associates digits of a related priority number one digit on an arbitrary bus.

In a system in which a device divides a common resource, a system generally uses a configuration of allocating a call to a resource while a plurality of related devices may request a call to the resource at a time. This is known. BACKGROUND OF THE INVENTION In data processing and packet switching systems, it is known to use a central allocation device or controller for allocating calls to a common data bus that interconnects multiple devices that may simultaneously request calls to the bus. The controller may be programmed with appropriate algorithms to allocate bus calls and use them according to some preferentially determined criteria that may be desirable. Although the central controller assignment device operates properly and performs its intended function, it is not always desirable because of the system inherent complexity resulting from the many interconnections required between each controller, bus and port. In addition, the malfunction of the controller causes a problem in reliability because it can paralyze the operation of the entire system. Systems with a central controller are described in US Pat. No. 3,983,540.

If bus assignments are requested at the same time, it is known in a distributed bus assignment configuration in which the interaction of the request port determines the bus assignment instead of using the controller for call determination. Such a distribution configuration is sometimes good because it avoids the high cost of the central controller configuration and the associated degradation of reliability.

According to this distribution allocation configuration, each port or unit that may request a call to a common bus or resource is assigned a fixed priority number consisting of a plurality of binary digits. The call is granted by priority number in case of concurrent request. During the bus line selection time, when more than one device or port requests a call at the same time, each requesting device sequentially applies the corresponding bit of the priority number to any bus simultaneously with the application of the corresponding bit by all other concurrent request ports. . As each bit is applied, each command port compares the size of the bit currently being applied to any bus with a logical combination of corresponding bits simultaneously applied by all concurrent request ports. If the request port currently has a specific relationship (equal or higher) to the bits applied to the bus by another request port, this operation proceeds and the port assigns the next bit of the priority number to any bus. Is authorized. One port removes it from circuit selection when determining that one or more other ports have a relationship (lower) to bits applied by another port indicating that they have a higher priority number. At that time, each port with a lower priority is removed from the line selection and no bits are applied to the bus.

This line selection operation continues, the remaining bits of the port priority number are applied to the bus by all remaining ports, the lower priority port is removed from the line selection, and the line selection interval at which the last bit is applied to the bus ends. Only the port with the highest priority at that time stays in the circuit selection state and it is recognized as a call to the bus.

Configurations of the type described above are described in US Pat. No. 3,796,992 and US Pat. No. 3,818,447.

The distribution line selection configuration described above works satisfactorily. However, its problem is that the priority number is fixed and the port call is determined by this priority number so that the port is a fixed priority with the most suitable port with the highest priority and the least suitable port with the lowest priority. Can be thought of as functionally arranged. In such a case, the call to the bus would not be justified, because the call to the bus would not be justified because a port with a port priority is always sent in case of concurrent requests. This improper allocation of ports may be allowed on any system, but the system has the problem of requiring legitimate calls by all ports.

This problem is solved by the present invention, and the system according to the present invention also includes a polarity control lead interconnecting the controller and the unit, and a first network in the controller to supply an inverted signal to the polarity control lead at a predetermined time. If there is an inverted signal on the polarity control wire, the superimposed network in response to inverts the corresponding digit of the priority number before the digits are superimposed simultaneously one digit on a random bus, and the comparison network in each request unit The digit value supplied on any bus is sequentially compared with the size of the corresponding digit supplied by each requesting unit, and the second network in each requesting unit is between the current digit of the arbitrary bus and the corresponding digit value supplied to any bus by the unit. When detecting the result of comparison specified in the above, subtracting itself from the line selection of the equipment call, the third network All digits of the first number of the support unit is to accept the call to the required equipment for the split request unit that remains in the line-selection state after the supply to any bus.

In addition, according to the present invention, flexibility in port priority is generated by providing a conductor called a polar conductor extending from the system controller to each port. The controller may apply a signal to the polarity wire at any time during the bus line selection period so that each current request port is assigned the reverse of the preferred digit assigned to any bus.

Suppose that ports with priority numbers 111 and 000 are being discussed at the same time, since port 111 has a higher priority number than port 000, the call to the bus would normally be made. However, in accordance with the present invention, the priority may be varied by the controller because the potential may be applied to the polarity wires to invert the bits that each pod might otherwise apply to the bus for a given circuit selection period. to be. Thus, port 111 applies bit 000 to the bus and port 000 applies bit 111. This ensures that port 000 comes first and makes a call to the bus. The controller may also operate in a mode in which the polarity bus is only active for a portion of the circuit selection period, for the first time applied digit. In this case the port with the specified priority 111 will apply bit pattern 011 to the bus and the port with number 000 will apply bit pattern 000 to the bus. This gives priority to systems where the first bit applied is the most significant bit of the port number.

The configuration described above solves the problem of conventional in that it provides more fair allocation of ports for calls to facilities or buses in the system, which increases flexibility and allows each port to be assigned a fixed priority number that determines bus-call priority. It is.

Figure 1 shows a packet switching system incorporating the present invention. In FIG. 1, a controller 100 having a polarity generator 122, a plurality of ports 110-1 through 110-n, a switch 107, a controller 100, and a plurality of ports 11 are interconnected. The bus is shown. These buses include a packet bus 105 which receives authorized data from the output 111 of each port. Packetbus 106 receives this data after it extends through switch 107 and applies it to the input 112 of each port. Clock bus 103 extends the signal shown in FIG. 3 from the controller to the port. The arbitrary bus 102 simultaneously receives the corresponding priority bits sequentially applied by each request port during the bus circuit selection time. Polarity conductor 101 applies a potential from controller 100 to port 110 at a selected time to apply the reverse of each digit of the priority number to bus 102.

Data processor 120-1, terminal controller 120-n and terminal 121 illustrate the type of equipment that may be used by the ports. As is common in packet switching, it sends over packetbus 105 and over packetbus 106 to input 112 of the port to which information is directed.

FIG. 2 shows the port 110 of FIG. 1 in detail. Each port includes an input / output interface 200, an input bus interface 210, and an output bus interface 220. The input bus interface 210 includes an arbitrary logic circuit 218 and a buffer 213 for applying data to the packet bus 105. The output bus interface 220 includes circuitry that allows a port to receive information from the packet bus 106.

Typically, the data processor 120 used by the port of FIG. 2 applies information from one packet to the other port via the input / output interface 200 to the other port and through the path 201. To FIFO 211. The FIFO controller 214 detects whether a complete packet has been received by the FIFO 211 and the bus path to the next circuit selection or any logic circuit 218 that acts next for a certain interval to allow the port to reach the bus. Send a request for. As soon as this arrival is made, the FIFO controller 214 applies the packet information it contains to the packet bus 105 via the buffer 213. This information includes header information that identifies the port on which the packet is being sent. After passing through the switch 107 on FIG. 1, the information passes through the path 112 of the receiving port to the packet bus, through its buffer 221 to the FIFO 227 and to its packet identifier 223. Is approved. The device 223 detects whether the current information in the FIFO 227 is actually directed to this port, and then the FIFO 227 passes through the path 202 and the I / O interface 200 by the FIFO controller 225. And outputs to the device used by the receiving port via path 117.

3 shows waveforms of timing signals and control signals applied to the ports via the clock bus 103. The upper signal is a positive frame pulse that identifies the beginning of each frame. Start the bus circuit selection interval with a frame pulse. The lower signal is a bit output signal and is used not only for controlling the input and output of data destined for the packet bus 105 from the port circuit, but also for circuit selection or for a number of control purposes during arbitrary intervals.

프리셋트 입력상에서 그리고 플립플롭(412)에 대한 입력상에서

로 반전된다. 플립플롭(410)상의 P신호는 플립플롭이 셋트상태(Q=HI)를 취하게 한다. S입력상의 저신호는 플립플롭(412)을 셋트시킨다. 플립플롭(412)의 셋팅과 그것의 Q출력상의 HI는 통로 (413)을 거쳐 NAND게이트(406)의 우측 입력을 인에이블시킨다. 이것은 시프트레지스터(400)로 부터 밝혀진 포트번호 비트들을 게이트(404,406)을 거쳐 임의비스(102)로 인가할 수 있도록 게이트를 인에이블시킨다.Details of the arbitrary logic circuit 218 of FIG. 2 are shown in FIG. At the beginning of the frame shown in FIG. 3, the initiation of a frame pulse on path 426 causes the designated port number to run in parallel from element 427 to path register 428 via path 428. When the port requests a PENDING signal, HI appears on the passage 216, and the start of this signal and the frame signal 426 is inverted to LO by the NAND gate 430. This LO is for flip-flop 410

On the preset input and on the input to flip-flop 412

Is reversed. The P signal on the flip flop 410 causes the flip flop to assume the set state (Q = HI). The low signal on the S input sets flip flop 412. The setting of flip-flop 412 and HI on its Q output enable the right input of NAND gate 406 via passage 413. This enables the gate so that the port number bits found from the shift register 400 can be applied to the arbitrary bits 102 via the gates 404 and 406.

The contents of the shift register are now revealed sequentially under the control of the clock pulses on the passage 425. The upper input of the gate 404 is low because it is low level on the bus 101 and thus the bit read out from the shift register 400 is applied to the left input of the gate 406 through the gate 4040 without changing. . The right input of gate 406 is enabled by the high level from the Q output of flip-flop 412. Thus, the bits received by the left input of gate 406 are inverted and applied to bus 102.

The non-inverted port number bit is also applied by the gate 404 to the lower input of the exclusive OR gate 409. The upper input of the gate 409 is connected to the bus 102. Each bit is read from the shift register, inverted by gate 406, applied to bus 102, and an exclusive OR gate 409 sends the current digit value on any bus 102 to gate 406. After inverting, compare how this port is placed on the bus. This comparison is explained in detail below. If not, the next digit is read from the shift register and applied to the bus 102 in the inverted form by the gate 406. There is no mismatch if the digits placed in the bus of FIG. 4 are the same or greater than the digits placed on the bus by other ports.

If there is a mismatch, the input of gate 409 is the same and the output of gate 409 goes LO. Mismatch is present when bus 102 is LO and the port signal from gate 404 is LO. This phase allows the port of FIG. 4 to apply O as the HI to the bus 102 from the gate 406 while the other port applies 1 as the LO to the bus. Since the bus is a hardwired gate, LO (1) applied from another port overwhelms HI (O) by the port of FIG. 4 and introduces the bus LO. Another port applying 1 as the LO to the bus is circuit selected and is accepted as a bus path because its authorized bus number bit is greater than the port number currently described. At the rising edge of the next clock pulse, the LO from the gate 409 on the D input of the flip-flop 410 is flipped so that the resulting LO output at its Q is applied through the passage 411 to reset it. Inverted from R to flop 412 to LO. The LO output at Q of reset flip-flop 412 extends through passage 413 to disable gate 406 from the bus by disabling its right input. Thus, the port of FIG. 4 does not arbitrarily select a bus under the mismatch described above.

The highest priority port with a pending request is a single port with flip-flops 412 set after all bits have been read from the shift register 400 through the passage 401 and extend through the gate 404. And is inverted by the gate 406 and applied to the bus 102. This port selects a random bus. Its flip-flop 412 is still in the set state at the time of the next frame pulse, and then flip-flop 412 drives its Q output high as a port select signal on passage 217. ).

The random scheme described above results in a port of fixed priority for the bus passage with the highest priority number having the highest port number. If the bus 105 occupancy is low enough, the fixed priority of this port is acceptable since very few ports are waiting for a bus call at any moment. As occupancy increases, performance becomes most critical during high occupancy conditions, resulting in the problem that performance should not be degraded.

Flexibility in port priority will be achieved in accordance with the present invention by the selective use of polarity conductor 101 to invert one or more port priority numbers read from the shift register during bus line selection time. Each port number has a sign P ₀ , P ₁ ... It is denoted by P _N (where P denotes 1 bit). Since this priority number is hard-wired in the element 427, each set P ₀ , P ₁ . P _N is special for each port. If the same bit inversion is performed on one or more bits of all ports, this particularity is not affected. Thus, form P ₀ , P ₁ . P _N is still special for all ports.

If the number of ports is N bits, there are 2 ^N ways to invert the auxiliary set of bits on all ports and to invert these bits. 2 ^N uses all of the different port priority arrays, so each port has the highest priority in one subband, and a second priority for one array. For other arrays, it has the lowest priority. This can be illustrated as the table below for N = 3.

The polarity bus 101 allows port priority to be flexibly changed from the polarity generator 122 within the bus 101. The simplest arrangement is to replace the priority bus for the entire alternating frame. If the port numbers are set sequentially, this results in two priority arrays, first by the size of the priority number and second by the inversion of the priority. This arrangement only provides a sufficient change of priority.

The polarity bus 101 is LO in non-inverting operation and HI in inverting operation. The polarity bus signal of the bus 101 is applied to the high input of the exclusive gate 404 via the gate 113 and through the gate 402. The LO, which is normally on passage 426, enables gate 402 on the bottom input to allow signals to pass through bus 101. It receives the port priority bit from the exclusive OR gate 404. For the non-inverting condition of the bis 101, the output of the gate 404 with the high input LO of the gate 404 and the port priority bit LO from the shift register is LO. First the output of gate 404 will be HI if the bus signal is HI for an inversion condition and the port priority bit is LO. Thus, the LO signal on the polar bus 101 applies LO to the high input of the gate 404 and allows the port priority bit from the shift register 400 to pass through the gate 404 unchanged. The HI signal on the polar bus at the top input of gate 404 inverts the shift register bit to which gate 404 is applied to the bottom input. This inverted bit is applied to the left input of gate 406 and is applied to the left input of gate 406 and inverted by gate 406 to bus 102. It is applied to the output signal of the exclusive OR gate 404 or to the bottom input of the exclusive OR gate 409. Thus, the port priority signal is sequentially applied to the gates 406 and 409 during any sequence so that the gate 409 can detect match or mismatch conditions for each digit applied to the bus 102 by the port. .

As described above, the port with the highest port number with the pending request remains set after all bits have been read through the passage 401 and applied to bus 102 by reading the output of the shift resist. This port surpasses non-mediation. The set state of the flip-flop 412 and HI on the Q output of the flip-flop set the flip-flop 412 on the guide edge of the next frame pulse. The setting of flip-flop 421 directs the port to be invoked by data service 105 by applying a signal to passage 217 at the Q output. Flip-flop 421 allows linear intervention to overlap time with data transfers associated with any cycle in the dictionary.

Full flexibility of port priority can be achieved by allowing the polar bus 101 to be operable through all 2 ^N sequences while the polar bus transition synchronized with the bit clock is maintained. There are two ways to get a 2 ^N sequence. The first method takes place sequentially by frame. This method in 2 ^N frames causes the entire set of priority arrays to cycle. Another method uses a linear feedback shift register to generate a pseudorandom bit string for each bit of each frame. After all, all 2 ^N priority arrays are used but not within 2 ^N frames.

The priority algorithm (every 2 ^N inversion pattern is used such that every port has a first priority once, a second priority once, etc.) can be proved as follows.

에 의하여 B_N…B₀로 변환된다.Assume the following instruction, ie P _N ... P ₁ = N Bit of the port number assigned to one bit These numbers are unique because no other number can have this port number. I _N … I ₁ = Sequence value on the polar bus, this same sequence goes to all ports. B _N ... B ₀ = Sequential value represented on any bus by one port, P _N ... P ₁ is an algorithm

By B _N … Is converted to B ₀ .

이며 포트번호 P_N…P₀가 모든 포트에 대하여 유일하기 때문이며 극성버스 I_N…I₀는 모든 포트에 대하여 동일하다.Given bus priorities are known as sequential B _N. Represented by B ₀ . For example, the first priority is 000... 000 and the second priority is 000... 001. The final priority is 111. 111. 2 ^N sequential I _N … for a given port to have some priority. There is only one of I ₀ . For example, a port having P ₃ P ₂ P ₁ = 1, which becomes the first priority (B ₃ B ₂ B ₁ = 000), requires that the polar bus sequence be I ₃ I ₂ I ₁ = 101. There is also only one polar bus sequence that makes the port a second priority, a third priority, and so on. Therefore, any given port will be once the first priority and once the second priority. When polarity bus through all 2 ^N possible reversal pattern sequence any bus B _N ... B ₀ is unique for all ports. No discrepancy will occur where both ports have the same bus priority at the same time. this is

Port number P _N. Because P ₀ is unique for all ports, the polarity bus I _N ... I ₀ is the same for all ports.

An additional subdivision that changes the packet switching priority arrangement is latched on to every pending bus request at any moment and will perform all these requests before any new request is given. This can be done because a flip-flop 422 is provided, which can be set to indicate the port request pending state, and when set, a "1" through the passage 423 is called a Snapshot Bit (SSB). The number 427 is stored as the most significant bit of the port before the most significant bit (MSB) of the given port priority number.

The flip-flop 422 that performs each port request is set during the snapshot time as described below. The first bit (SSB) gated on any bus for each subsequent best selection period is the SSB of the flip-flop 422 of each port and has a request to pending the last time given a snapshot. Since the SSB has the highest priority, all ports with this set of bits are given priority to all other ports until each port with a set of flip-flops 422 is performed.

A new snapshot is given when all ports are performed. At this time and the final time of the SSB for this line selection, the random bus is LO because the port does not have a flip-flop 422 set, and the SSB is zero and the random bus through the inverting gate 406 is HI. This HI on the passage 114-1 is applied to the top input of the gate 417. If the port has a pending request signal 216 (HI), the bottom input of AND gate 417 is HI and the output of AND gate 417 is HI. The trailing face of this HI and framepulse drives the output of Q of flip-flop 418 HI. This is set in each port having a pending request signal on the passage 216 when the bus 102 is HI for SSB time.

As a result, the HI output of the flip-flop 422 of the port is stored in the port's shift register via the passage 423 as SSB. Only ports with a set of flip-flops 422 will be performed. The next snapshot, generated as HI when all these ports are performed, is applied to bus 102 when the SSB of each shift register is zero.

Selection of the port for bus access clears flip-flop 422 when flip-flop 421 is set. The AND gate 402 is suppressed to block the polar bus 102 by the passage 426 by inverting the snap shot applied to the bus 102. The start of the frame pulse through the passage 426 is inverted at the bottom input of the suppression AND gate 402 to generate the LO output signal to the exclusive OR gate 404. This prevents the shift register 400 from accepting the SSB bit from the flip-flop 422 through the passage 423 by the exclusive OR gate 404 of the SSB bit.

5, 6 and 7 illustrate alternative arrangements for implementing the polarity generator 122 of FIG. 5 shows one flip-flop whose Q output is driven by a frame clock that is HI and LO alternately for sequential frames. This applies optional HI and LO on the frame to the top input of the exclusive gate 404. This passes through a shift register bit in which the gate 404 does not change when inverting the shift register for a frame where the top input is LO for the frame and the top input is HI.

6 shows the polarity of a flip-flop including a pseudorandom generator driven by a bit clock. This circuit randomizes the potential applied to the polarity bus of successive clock signals. In other words, randomize the state in which the various shift register beaters are inverted and randomize the port steps for calling the bus 105.

7 shows a role including a counter 700 and a ROM 701. The counter is driven by a bit clock to apply an address signal to the ROM, and the ROM reads the contents of the address addressed to the polar bus in response to the acquisition of each address signal. Any desired arrangement for changing port priority may be programmed into the ROM by proper programming of the ROM.

Claims (8)

A system for allocating a call to a division request facility among a plurality of units 110 in which each unit has a unique n-digit priority number 427, which is a system controller 100 and an arbitrary bus 102 interconnecting all units. And a network 406 for simultaneously superimposing corresponding digits of the relevant priority number 427 on each bus in sequence in each unit 110 requesting a call to the division requesting facility 105 on each bus in sequence. In the system, the inversion signal is supplied to the polarity control lead 101 and the polarity control lead 101 at predetermined time intervals so that the inverted signal is placed on the polarity control lead. Is present in the first network 122 in the controller 100 that inverts the corresponding digit of the priority number before the overlapping network 406 responds to sequentially overlap each digit on any bus. Arbitrary buses in the comparison network 409 in each request unit for sequentially comparing the digit values on any bus when applied to the bus and the magnitude of the corresponding digits applied by each request unit, and the comparison network 409 in the request unit. A second in each requesting unit to eliminate confusion in the facility call when detecting the result of a prescribed comparison between the current digit value of 102 and the value of the corresponding digit currently applied to any bus 102 by the unit 110. A second network (412) and a third network for approving the call of the splitting request facility to the request unit (110) which remains confused after all of the digits of the priority numbers of the remaining units are applied to the arbitrary bus (102). 421), the system for allocating a call to a split request bus. In the system according to claim 1, a priority number having a plurality of binary digits and an overlapping network 406 sequentially generates a logical union corresponding to a priority number digit which simultaneously applies a request unit to an arbitrary bus. And a gate network. In the system according to claim 2, each unit 110 is arranged with a coupling register 404 and a shift register arranged to apply a priority digit to the coupling network 404 sequentially by each digit in a prescribed order. 400 and enabling network 430 to actuate coupling network 404 by being operated by the associated unit during the request for facility call to supply digits sequentially from shift register 400 to arbitrary bus 102. 412, and a third network (410, 412) for disabling the enabling network (430) in response to a comparison network (409) for detecting a prescribed comparison result. In the system according to claim 3, the coupling network 404 has a logic gate, and the enabling circuits 430, 412 can be operated in a first state by an associated unit for operating the logic gate. And a dual state device (412) capable of operating in a second state by means of three circuits (410, 412). 5. The system according to claim 4, wherein the comparison network comprises a logic gate (409) which responds together to a signal from an arbitrary bus (102) and a signal from a shift register. 6. The system according to claim 5, wherein the enabling circuit comprises a logic device responsive to a control signal from the associated unit and a comparison network for controlling the state of the logic device. A method of allocating a call to a split request facility when a plurality of units simultaneously request a call among a plurality of units each having a unique n-digit call number for determining a call. Supplying an inverted signal to the polarity control lead of the unit, and sequentially, one digit on each bus, the corresponding digit of the priority number of each unit requesting the equipment call simultaneously when the inversion signal is not currently supplied to the polarity control lead. Overlapping at the same time, sequentially superimposing the reverse digits of each digit of the priority number of each unit requesting the facility call each time an inverted signal is simultaneously applied to the polarity control lead, one digit on an arbitrary bus; The digit value on any bus is matched with the corresponding digit value authorized by each request unit Comparing sequentially, eliminating equipment call confusion in any requesting unit when detecting a prescribed comparison result between the digit value of any bus and the corresponding digit value subsequently applied by one unit, and all assigned Approving a facility call for a unit that remains in a chaotic state after a priority digit has been applied to an arbitrary bus. 8. A method according to claim 7, further comprising the steps of: defining a snap time, switching a logic device in each unit requesting a call during the occurrence of the snap time from a first state to a second state; Applying a snap bit to the bus as the most significant bit of the assigned priority digit in each facility requesting a call, and the logic within each unit to which the call to the facility was granted while applying the snap bit to any bus. And switching the device from the second state to the first state.

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