SU1515170A1 - Device for interfacing processors in computer system - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor computing systems for implementing task interaction. The purpose of the invention is to expand the functionality by switching processors when implementing highly coupled parallel algorithms. The device contains a group of interface blocks 2 amplifiers, a block 4 priority registers, a node 3 switching connections, including a switching node, a process priority node, a group of control registers, three groups of elements And, the first priority node of the active process, two groups of pulse drivers, buffer registers and readiness, two groups of AND blocks, two groups of control triggers, a group of comparison circuits, three OR elements, an AND element, a control trigger, a pulse generator, and a process selection node consisting of Rupp elements I. The new device is to administer a compound switching unit start trigger, of the OR gate, the delay element, two elements, and the second node priority active process, and a process selecting unit - a group of AND gates and two OR groups of elements. 1 hp f-ly, 6 ill.

Description

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The invention relates to computing and can be used in multiprocessor computing systems for implementing task interaction.

The aim of the invention is to expand the functionality by switching processors in the implementation of highly coupled parallel algorithms.

Figure 1 shows the block diagram of the proposed device; figure 2 is a functional block diagram of the priority registers; in fig. 3 is the same for the connection node of the connection; 4 is a diagram of a processor selection node; figure 5-. same, priority node; figure 6 - the same switching node.

The device (Fig. 1) contains buses 1 of a standard communication interface, IH-interface units 2 amplifiers, connection switching node 3, block 4 of priority registers, transfer bus 5, reception bus 6, request lines 7, request buses 8, buses 9 outputs block 4 priority registers.

Unit 4 of the priority registers (figure 2) contains the switch 10 and the group of registers 11 priority.

Connection switching node 3 (FIG. 3) contains a group of control registers 12, a first group of elements AND 13, a processor selection node 14, a synchronous input 15, a control input 16, a group of control inputs 17, a group of request inputs 18 and a group of outputs 19 node 14, buffer register 20 requests, the first group of pulse shapers 21 (differentiating elements), processor priority node 22, the second priority processor priority node 23, the first group of AND 24 elements, the third group of AND elements 25, the first group of control triggers 26, first element 27, the second group of pulse formers 28, the first delay element 29, the third delay element 30, the control trigger 31, the fourth element OR 32, the third element AND 33, the second group of elements AND 34, the second element And 35 the buffer register 36 ready, the second the group of blocks of elements AND 37, the second element OR 38, the group of elements 39 comparison, the first element AND 40, trigger 41, the third element 1S11 42, the first node 43

Q

-with

20

25

thirty

DO 45 CQ

55

theta of the active processor, the second delay element 44, the second group of control triggers 45, the switching node 46, the outputs 47 of the flip-flops 26 (first address inputs of the node 46), the OUTPUT group 48 of the formers 21 (first reset inputs of the node 46), the output 49 of the delay element 44 (strobe input of node 46), group of outputs 50 of driver 28 (second reset inputs of node 46), outputs 51 of flip-flops 45 (second address inputs of node 46), first 52 and second 53 control inputs of the device, outputs 54 of register 20 and. 55 pulse generator.

Node 14 processor selection (figure 4) contains the second group of elements OR 56, the first 57 and the second 58 groups of elements AND, respectively, and the first group of elements OR 59.

Processor priority node 22 (Fig. 5) contains a group of decoders 60, a group of elements OR 61, a group of elements AND 62, an encoder 63 and a group of elements 64 comparison.

Switching node 46 (FIG. 6) contains channels 65, each of which includes the first 66 and second 67 groups of elements AND, a register 68 and a switch 69 and a group of elements OR 70 in the ser.

The device works as follows.

When organizing processes in a computing system, each of them is assigned the required number of processors. At the stage of planning the calculations by the operating system to determine the sequence of organization of interprocessor connections within the created processes, each of them is given priority by the binary codes of the natural number of numbers, with the highest priority being given to the process with the lower priority code. Each processor of the same process is given the binary priority code of the given processor and the same task (process) number. This enables the organization of exchanges signal requests and readiness to accompany the process number. In each process, a number of processors (active) form request signals, and the rest of its processors (passive) form signals of correspondence. These signals are accompanied by a process number and

are linked in the corresponding register 12 (FIG. 3).

Each control register 12 contains two triggers storing request and readiness signals, and a register for storing the binary code of the process number.

The priority assignment function may be charged to any of the processors included in the computing system that is currently central. In so doing, block 4 is treated as a subscriber to the processor assigning priorities. The processor issues a priority code, which through the corresponding interface unit 2 enters via buses 5 to the input of switch 10 (Figures 1 and 2) and further to the corresponding register 11 via the control signal on lines 7.

The interprocess exchange begins with the communication phase between the processors assigned to the process. The establishment of communication takes place in accordance with the priorities assigned to the processes. The selection of the priority process is as follows.

The initial state of the device is characterized by the fact that triggers 31 and 41, registers 20 and 36, triggers 26 and 45 (Fig. 3), registers 68 of channel 65 (Fig. 6) are set to O (installation circuit not shown).

If it is necessary to establish communication with aktigzny processors on buses 8, registers 12 register request signals and process number codes and passive processors on bus 8 readiness signals and process number codes, and input 53 sends a trigger signal that sets the trigger 41 to state 1.

Since the triggers 31, 26 and 45 are in zero states, in registers 20 and 36, using the open elements 13 and 34, the state of the triggers T and T of register 12 is monitored. signals through the corresponding elements OR 27 and 38, the element AND 40 is opened, and the first pulse of the generator 55, the trigger 31 is set to state 1. The elements 13 and 14 are closed, which fixes the signals in the registers 20 and 36 in the interprocessor establishment cycle.

151706

The single signals from the outputs of the register 20 enter the node 22 through the inputs 54, and the single signal from the single output of the trigger 31 opens the elements AND of the second priority node 23 of the active process. At node 22 (FIG. 5), the priority codes are converted to unitary ones by means of open Q corresponding to the Q 54 inputs. The identical outputs of the decoder are combined by the elements of the same name OR 61. With the help of the elements AND 62 connected with the outputs of the elements 5 OR 61 according to the priority scheme,

priority is allocated. younger unit and the formation of a unitary code on the inputs of the encoder 63, converts it into binary. 20 By comparing elements 64, a position code of the number of active processors of the priority process is determined. In this case, the numbers of the excited outputs 18 of the node 22 correspond to 25 numbers of the active processors, and their number to the number of active processors requiring the establishment of a connection within the priority process. Using the node 23 of the priority active process from several requests of the priority process, the crash of its left single signal is made from the position code from Loose DON 18. This signal opens the elements AND blocks 24 and at the combined outputs of blocks 24 a binary code is generated priority process. This code is fed to the inputs of the comparison elements 39. The other g0 inputs of the comparison elements 39, through the corresponding open readiness signals of register 36, blocks 37, receive codes for process numbers, the passive processors of which have set g5 readiness signals for exchange.

In this case, two cases are possible: readiness signals are received into register 36 from passive processors that are not related to the selected priority process 50; register 36 records readiness signals for passive processors that belong to an allocated priority process.

In the first case, at the outputs of comparing elements 39, a zero code is set, by which elements And 25 are closed through the ILTIi 42 element, and And 33 elements and And 58 elements at node 14 are opened by inverse inputs (Fig. 3 and 4).

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After a certain time, determined by the delay element 29, all the triggers of the registry 20 related to the priority process are set to the state O by means of the evil 14 processor selection as follows. Let the priority processor include signals in T 20 and 20. Under these conditions, at outputs 18 and 18 of node 22 there are single signals that form the position code: 10 ... 01. With node 23, a unitary code is formed at the outputs 17: 10 .- .. CO. At node 14, one. With the input signal from input 1, elements AND 57 are opened at the first input, element I-58, at the third direct input and through elements OR 56 - through the third direct inputs, elements H 58, starting with the second. At input 18 ", the element And 58п-) is open at the first direct input. Thus, when a signal is received from the synchronous input 15 in node 14, single signals are formed at the output 25 of the element 57 and at the output of the element OR 59l., Coming from the output of the element 58 and 58, signals from the outputs 19, and 19 | 20, and 20p are set to zero states. In this case, if in the register 20 there are request signals, then at the output of the element OR 27 a single signal is held, by which the elements AND 33 and 35 are closed by inverse inputs. As a result, the trigger 31 remains in a single 35 state and, according to the second pulse of the generator 55, the next device operation cycle is organized.

In the second case, the AND 25 elements are opened by the single signal from the output of the OR 42 element and closed at the inverse elements of the AND 58 elements at node 14. At the same time, if there are several single signals at the outputs of the comparison elements 39, the left-most unit of the positional code output signals of the elements 39 comparison. The delayed signal from the output of the delay element 29 is set to state 1, the corresponding triggers 26 and 45 to the state O through the corresponding element 34 and the register register 36 with the same name and the corresponding register register 20. Let 55 be the priority process in this case mc T 20.j and T 20}. Under these conditions, the inputs are 182, 18 and 172.

thirty

five

0 5

0

1708

node 14 there are single signals. With a single signal from input 18, the element AND 57 is opened at the first input, the elements of AND 58 are closed at the inversion inputs. Therefore, a pulse from synchronous input 15 only at the output of element And 57 forms a single signal; w, coming through element ИШ1 59I to output 19 of node 14. This signal sets the state O to the trigger 20 of the register 20. If, after setting to the state O, the register is 36, allocated for interprocessor communication, it does not have ready signals from passive processors, a single signal from the output of the OR element 42 is removed. In this case, AND 33 is uncoupled at the inverse input with a zero signal from the output of the OR 42 element, and with a single signal from the output of the OR element 27 at the direct input it is held in the closed state. In addition, AND element 35 is open at the direct input with a single signal from the output of the element OR 27 and at the inverse input with a zero signal from the output of the OR element 38. Therefore, by an additional delayed pulse, delay element 30 causes the trigger 31 to become zero. and readiness respectively in registers 20 and 36 through the open elements And 13 and 34.

Similarly, the trigger 31 is set to the zero state, when, after establishing the connection between the active and passive processors, the registers 20 and 36 are in the zero states, through the And 33 element.

If, however, after setting to the state of the bit of register 36 allocated for interprocessor communication, it contains signals of readiness of processors that are not related to the priority process, as indicated by the signal at the output of the element OR 42, elements 33 and 35 are closed at inverse inputs with single signals, respectively, from the outputs of the elements OR 38 and OR 27. Therefore, the trigger 31 remains in the single state n.

Element AND 40 is held in the open state by single signals from the outputs of elements OR 27 and 38, therefore the generator 55 pulse is set in the manner described above.

f5

20

25

It is in the state of the register register 20 priority process. This ensures the establishment of interprocessor communications for the next priority process in the presence of request signals and readiness in registers 20 and 36.

The output signals of the flip-flops 26 and 45 are used to switch the inputs and outputs of the active and passive processors in the switching unit 46.

Let the triggers 26, and 45 c be set to one. This means that, according to the request, the outputs of the first processor must be connected to the inputs of the nth processor, the outputs of which, in turn, must be connected to the inputs of the first processor. This task is performed by node 46 as follows. A single signal from input 47 ((FIG. 6) opened elements And 67 in channel 65, and element And 66, in canape 65f ,. A single signal from input 51 opened element And 67 f,., In channel 65, and elements And 66 in channel 65 ,. Through the delay time determined by element 44 (Fig. 3), triggers 68 "in channel 65 and 68. in channel 65" are set to one. At the same time, buses 5 of the first process are connected by switch 69 to the buses 6 ' and the buses 5, with the switch 69, are connected to the buses 6., thereby providing two-way communication of the first processor 35 with the p-n2.

The pulse repetition period of the generator 55 is selected based on the parameters of the delay elements 29 and 44.

At the end of the exchange, the request and readiness signals are removed. In this case, the corresponding triggers of register 12 are set to state O. The potential drops at zero outputs are differentiated by the corresponding elements 21 and 28, the positive signals from the outputs of which set the zero trigger conditions 26 and 45 to zero state and, at node 46, the trigger 68 of the corresponding channels 65 through OR elements 70.

If it is necessary to create new processes, redistribute priorities to processes or in other cases when the need to set up interprocessor communications is excluded, then a stop signal is sent to input 52, through which start trigger 41 is set -

thirty

-40

45

55

to

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20

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35

151517010

is brought to the state O, and the pulses of the generator 55 are stopped.

To use the device again, it is reset. Thereafter, a start pulse is applied to the input 52.

Claims (2)

Claim 1. Device for communication of processors in a computing system, containing a group of interface blocks of amplifiers, the inputs / outputs of which are a group of inputs / outputs of the device for connection to the inputs / outputs of the respective processors of the computing system, a block of priority registers, a group of information and the group of synchronous inputs of which are connected respectively with the information-1 and outputs and the output signal of the request of the interface blocks of the amplifiers of the group, the connection switching node, including the comm node tions, the information inputs of the group and the outputs of which are connected respectively to the information outputs of the group and the inputs of the interface blocks of the group amplifiers, the process priority node, the group of information inputs of which are connected to the output group of the priority register block, the control register group, three groups of I elements, the first priority node active process, two groups of pulse formers, a buffer register of requests, a buffer register of readiness, two groups of blocks of AND elements, two groups of control trigger , group of comparison elements, first and second delay elements, first, second and third OR elements, first AND element, control trigger, process selection node consisting of the first AND group, whose second inputs are connected to the synchronous input of this node, and pulse generator The information inputs of the control registers of the group are connected to the input-output of the corresponding interface 50 amplifier blocks, the first and second address inputs of the switching node are connected respectively to the single outputs of the first and second trigger points. Ora groups, zero inputs of which are respectively connected to first and second inputs and reset switching node through the first and second pulse shapers sootvetstvukitsie thirty 40 45 55 groups - to the inverse outputs of the request and readiness bits of the control registers of the groups, the direct outputs of the request bits of which are connected to the first inputs of the AND elements of the first group, and the outputs of the number code bits to the information inputs of the blocks of the first and second groups of elements, outputs which are connected respectively to the first and second inputs of the group comparison circuits, the output of the first delay element is connected to the second inputs of the AND elements of the third group, with the synchronization of the inputs of the first priority node of the active process and the node you The view of the process and through the second delay element - with the gate input of the switching node, the outputs of the elements of the third and first groups are connected respectively to the single inputs of the control triggers of the first group and the buffer query register, the output group of which is connected to the group of permitting inputs of the processor priority node and the group of inputs of the first element OR, the first input of the group of control outputs of the processor selection node is connected to the zero input of the first bit of the buffer register of requests, the single trigger input of the pack The control unit is connected to the input of the first delay element and the output of the first element AND, the first, second and third inputs of which are connected respectively to the output of the pulse generator, the first and second elements OR, the input group of which is connected to the control inputs of the blocks of elements AND of the second group the buffer readiness register, the group of single inputs of which is connected to the outputs of elements AND of the second group, the first inputs of which are connected to the single outputs of the readiness bits of the control registers of the group, the first The control outputs of the first and second groups of riggers are connected to the second inputs of the AND elements of the first and second groups, a third of them are connected to the zero output of the control trigger, the third inputs of the AND elements of the third group are connected to the output of the third OR element, whose input group is connected with the outputs of the group comparison circuits and with the group of request inputs of the first priority node of the active process10 15 20 25 A group of BL1Codes of which is connected to the single inputs of the control triggers of the second group and the group of zero inputs of the buffer register READINESS, which, in order to extend the functionality due to the switching of processes during the implementation of strongly coupled parallel algorithms, are entered into the switching node of the connection trigger trigger, the inputs of which are the control inputs of the device, the fourth element of the IPD, the third delay element, the second and third elements AND, the second priority node of the active process The synchronized input of which is connected to the single output of the control trigger, the output group of the process priority node is connected to the request input groups of the processor selector node and the second priority node of the active process, the output group of which is connected to the control inputs of the I unit blocks of the first group, to the first inputs elements of the third group and to the group of control inputs of the processor selection node, the control input of which is connected to the output of the third element OR and the inverse inputs of the third element AND, direct whose input is connected to the output of the third delay element, the connected input ;; the output of the first delay element, and with the portions the direct input of the second element And, the inverse input of which is connected to the output of the second element And, and the second direct input connected to the outputs of the first element tLTHi and the second inverse of the third And, the output of which is connected to the first the input of the fourth element S1I, the second input of the second element I connected to the output, and the node with the zero input of the control tripper, the single output of the start trigger is connected to the fourth input of the first element I. 2. The device of claim 1, about tl and - -50, in that the processor selection node further comprises a second group of elements AND and two groups of OR elements, the synchronization input is connected to the second direct input of 55 elements AND the second groups, inverse inputs of which are combined with the control of the professor's choice node, the first input of the control group 35 40 45 Ve 3 Fy 54 ft FIG. five