JPS5851456B2 - Multi-route control method for remote monitoring and control equipment - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention uses one remote monitoring and control device to control a large number of control consoles and computers installed in a large number of facilities, such as an expressway centralized monitoring and control system. , relates to a multi-route control method performed from a higher level system.

[Background of the invention]

When performing multi-route control, if a transmission word is fixedly assigned to the control signal of each control route, the same length of transmission time for one cycle is required even when no actual control is performed. The time required for control was longer, which was a problem.

One solution to this problem is one that incorporates priority processing control.

In this method, when there are a plurality of control routes that require actual control to be performed by the priority processing circuit, the order of transmission is determined in advance, and the control signals from each route are sequentially transmitted one route at a time.

In this case, if the number of control routes that are to be actually controlled at the same time increases, the waiting time for routes with lower priority becomes longer, which is a problem in systems with a large number of control routes.

[Purpose of the invention]

An object of the present invention is to provide a multi-route control system for a remote monitoring and control device that can perform multi-route control at high speed.

[Summary of the invention]

The present invention focuses on the fact that control signals from multiple routes can be transmitted simultaneously and continuously by using subcommutation (hereinafter referred to as subcommutation), and furthermore, without fixing the sampling of data transmitted using subcommutation,
By sampling and transmitting only the data of the route to be actually controlled, the sampling period is shortened and multi-route control is made faster.

In other words, if the actual control request is for only one control route, the transmission data of the same route is assigned to the subcommission word and transmitted every cycle, and if there are multiple routes, the transmission data of one route is sequentially transmitted in each transmission cycle. Transmission data is assigned to a subcomi word and transmitted.

[Embodiments of the invention]

Figures A and B show transmission formats according to the present invention.
B shows a case where there are transmission requests from three routes: 1161, A3, and An.

In the present invention, as is clear from FIGS. 1A and 1B, when there is a transmission request only from the A1 route, the data of the Ni1 route is assigned to the subcommission word following the synchronization signal SYC and transmitted, and the AI, A3, When there is a transmission request from An, in the first cycle, the data of the A1 route is sent to the subcommitment word following SYC, in the second cycle, the data of the A3 route is sent to the subcommitment word following SYC, and in the third cycle, the data is sent following SYC. Data of the An route is assigned to the subcommitment word, and in the fourth cycle, data of the A1 route is assigned to the subcommitment word following SYC again for transmission.

Although not shown from the fifth cycle onwards, unless the transmission request is canceled, AI, A3゜An, m are repeated.
It is transmitted as 1, A3, An...

FIG. 2 is a circuit diagram of an embodiment of the present invention, which will be described in detail below with reference to the time chart of FIG.

In FIG. 2, reference numeral 1 denotes a clock generation circuit, and a clock output 1a is inputted to one input terminal of an AND gate 2 and a transmission counter 11.

The output of an inverter 10, which will be described later, is input to the other input terminal of the AND gate 2, and only when the output of the inverter 10 is logic "1", the clock 1a is output as is.

The output of the AND gate 2 is inputted to the subcommit counter 4 via the OR gate 3.

The sub-commission counter 4 is incremented by the output 3a of the OR gate 3 and sequentially A I as shown in FIG.

Selection pulses such as A 2 , A 3 . . . An are output.

The concrete contents of the subcomi counter 4 include, for example, a binary counter that counts the output 3a of the OR gate 3, and a decoder that decodes the contents of the binary counter and outputs a single pulse.

Output Al a of subcomi counter 4, A2 a...
- Ana are AND gates 5-1 and 5-2, respectively.

. . 5-n, and the corresponding control routes A I and 16.2 are applied to the other input terminals of AND gates 5-1, 5-2, . . . 5-n, respectively.
...A (transmission request from 1 REQI, REQ2.-R
EQn is applied.

Therefore, the output of the subcomi counter 4 A 1 a =j/
6. When n a matches the transmission requests REQI to REQn from each control route configuration 1 to An, the AND gate 5-
Any one of 1 to 5-n turns on, and the OR gate 9
, the AND gate 2 is locked via the inverter 10, so the clock pulse 1a is no longer output from the AND gate 2, and the subcomi counter 4 stops incrementing.

Furthermore, the corresponding AND gate 6 (6-'l-6-n) is opened by the output of the AND gate 5 (5-1 to 5-n), and the control route from which the transmission requests REQI to REQn are output is opened. The transmission data (DI to Dn) is OR gate 7, AND
It is output to the parallel-to-serial converter circuit 12 via the gate 8.

Specifically, the transmission data is synchronized by the AND gate 8 using the word address timing 11b from the transmission counter 11, and is transmitted via the parallel-to-serial conversion circuit 12.

When one cycle is completed, a signal 11a of 1 pulse/cycle from the transmission count 11 is inputted to the subcommit counter 4 via the OR gate 3, and the subcommit counter 4 increments by one.

As a result, the coincidence established in the AND gates 5 (5-1 to 5-n) is released, so the clock pulse 1a in the AND gate 2 is also released, and the subcomi counter 4 receives the next transmission request A. It is incremented until it matches (REQI to REQn).

In this way, when the transmission data matches the transmission request REQ of the next control route, the transmission data is transmitted via the parallel-to-serial conversion circuit 12 as in the previous time, and by repeating this sequentially, the control route with the transmission request is transmitted. The sampling period is the shortest since only the transmission data of 1 is transmitted.

FIG. 3 shows waveforms of various parts when the control route AI and the control route A3 are shifted in time and the transmission requests REQI and REQ3 are issued.

At the output 12a of the parallel-to-serial conversion circuit 12, SYC is a synchronization signal, which is a synchronization signal from a synchronization signal generation circuit (not shown) that is set and transmitted to the parallel-to-serial conversion circuit once per cycle. .

Although the specific internal circuit of the transmission counter 11 is not shown, the transmission counter 11 counts the clock pulses 1a, outputs the transmission clock 11c, and outputs a fixed number of transmission clocks 11c corresponding to the subcommission data word. The signal 11b is output by counting, and once per cycle.
The transmission counter 11 and the above-mentioned sub-commission counter 4 having such a function are well known.

The feature of the embodiment shown in FIG. 2 is that the OR gate 9. Inverter 10. They are a locking mechanism using an AND gate 2 and an unlocking mechanism using an OR gate 3.

〔Effect of the invention〕

According to the present invention, control signals (transmission data) for multiple routes are transmitted continuously using subcommission words, so there is no waiting time while controlling other routes, and simultaneous control of multiple routes is possible. Of the route control signals (transmission data), only the actual control signals (data requested to be transmitted) are transmitted, so the sampling time is shortened, and a high-speed multi-route control system is realized.

[Brief explanation of drawings]

1A and 1B are diagrams showing an example of a transmission format according to the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a time chart for understanding the operation of FIG. 2. 2.5 (5-1 to 5-n), 6 (6 to 1 to 6-n)...
...AND gate, 3.9...OR gate, 4...Subcomi counter, 10...
... Inverter, 11 ... Transmission counter, 1
2... Parallel to serial conversion circuit.

Claims (1)

[Claims] 1. In a multi-route control system in a remote monitoring and control device, in which transmission data from a plurality of control routes is sequentially selected based on the output of a subcomi counter and transmitted in synchronization with the transmission clock from the transmission counter, Prohibition means for prohibiting clock input to the subcomi counter when the subcomi counter transmits transmission data of a specific control route based on a transmission request, and a means for incrementing the subcomi counter for each cycle including transmission data. A remote monitoring and control device characterized in that a canceling means for canceling a state in which clock input is inhibited is provided, and only transmission data of a control route for which a transmission request is made among a plurality of control routes is transmitted by subcommission transmission. Multi-route control method.